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    High speed CMOS image sensor circuits with memory readout
    12.
    发明授权
    High speed CMOS image sensor circuits with memory readout 有权
    具有块存储器读数的高速CMOS图像传感器电路

    公开(公告)号：US07659925B2

    公开(公告)日：2010-02-09

    申请号：US11243239

    申请日：2005-10-04

    申请人： Alexander Krymski

    发明人： Alexander Krymski

    IPC分类号： H04N5/228 ,  H04N3/14 ,  H04N5/335 ,  H01L27/00 ,  H03M1/12

    CPC分类号： H04N5/32

    摘要： An image sensor circuit includes a pixel array, a plurality of column analog-to-digital conversion (ADC) circuits, and at least two memory blocks. Each column ADC circuit is connected to receive analog pixel signals provided from corresponding pixel circuits of the pixel array, and is configured to convert the received analog pixel signals into digital pixel signals. Each memory block is connected to receive digital pixel signals provided from corresponding column ADC circuits of the plurality of column ADC circuits. At least two of the at least two memory blocks are connected to receive digital pixel signals that are provided from corresponding column ADC circuits that are located to a same side of the pixel array. Each memory block of the at least two memory blocks includes a plurality of memory cells, one or more sense amplifiers connected to the memory cells by a readout bus, and a memory controller.

    摘要翻译： 图像传感器电路包括像素阵列，多个列模数转换（ADC）电路和至少两个存储器块。 每列ADC电路被连接以接收从像素阵列的相应像素电路提供的模拟像素信号，并且被配置为将接收到的模拟像素信号转换成数字像素信号。 每个存储块被连接以接收从多个列ADC电路的相应列ADC电路提供的数字像素信号。 连接至少两个存储器块中的至少两个以接收从位于像素阵列的同一侧的相应列ADC电路提供的数字像素信号。 所述至少两个存储器块的每个存储块包括多个存储器单元，通过读出总线连接到存储器单元的一个或多个感测放大器和存储器控制器。

    IMAGE SENSORS AND DUAL RAMP ANALOG-TO-DIGITAL CONVERTERS AND METHODS
    13.
    发明申请
    IMAGE SENSORS AND DUAL RAMP ANALOG-TO-DIGITAL CONVERTERS AND METHODS 有权
    图像传感器和双RAMP模拟数字转换器和方法

    公开(公告)号：US20090273500A1

    公开(公告)日：2009-11-05

    申请号：US12434602

    申请日：2009-05-01

    申请人： Alexander Krymski

    发明人： Alexander Krymski

    IPC分类号： H03M1/12

    CPC分类号： H03M1/144 ,  H03M1/56

    摘要： Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

    摘要翻译： 双路斜坡模数转换器和方法允许对模拟信号进行模数转换。 各种双斜坡模数转换器和方法允许将模拟信号和粗斜坡施加到比较器的相同输入端，以及向比较器的另一输入端施加精细斜坡。 一些双斜坡模数转换器和方法允许将模拟信号，粗斜坡和精细斜坡应用于比较器的相同输入。 各种双斜坡模数转换器和方法允许将模拟信号施加到第一比较器的输入，通过粗斜波开关将粗斜坡施加到第一比较器的输入端，将模拟信号施加到 第二比较器，并且向第二比较器的另一输入端施加精细斜坡。

    Circuits and methods with comparators allowing for offset reduction and decision operations
    14.
    发明授权
    Circuits and methods with comparators allowing for offset reduction and decision operations 失效
    具有比较器的电路和方法，允许偏移减少和决策操作

    公开(公告)号：US07400279B2

    公开(公告)日：2008-07-15

    申请号：US11777905

    申请日：2007-07-13

    申请人： Alexander Krymski

    发明人： Alexander Krymski

    IPC分类号： H03M1/06

    CPC分类号： H03M1/0607

    摘要： Circuits and methods may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section.

    摘要翻译： 可以通过使用补偿比较器输入偏移对比较器决定的影响的ADC来改善电路和方法。 通过在ADC的输入端和ADC的比较器部分之间使用放大器部分放大提供给比较器输入的信号，从而减小比较器偏移对比较器判定的影响，可以在ADC中实现偏移补偿。 比较器部分可以是自动调零比较器部分，其能够执行偏移减小操作以在其输入处提供的电容器处存储偏移补偿值。 放大器部分可以是具有一个或多个放大器级的自动调零放大器部分，其能够执行偏移减小操作以在其输入处提供的电容器处存储偏移补偿值。 偏移补偿也可以使用没有前一放大器部分的自动调零比较器部分来实现。

    Method and apparatus for pixel signal binning and interpolation in column circuits of a sensor circuit
    15.
    发明授权
    Method and apparatus for pixel signal binning and interpolation in column circuits of a sensor circuit 有权
    传感器电路的列电路中的像素信号合并和插值的方法和装置

    公开(公告)号：US07319218B2

    公开(公告)日：2008-01-15

    申请号：US11601749

    申请日：2006-11-20

    申请人： Alexander Krymski

    发明人： Alexander Krymski

    IPC分类号： H01L27/00 ,  H04N5/217

    CPC分类号： H04N5/347

    摘要： A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples analog pixel and reset signals from different sensor circuit column lines. Once a predetermined number of column lines are sampled in the binning circuit, the sampled pixel signals are averaged together in one operation, while the reset signals are averaged together in another operation.

    摘要翻译： 一种分级电路及相关方法，其中来自传感器电路中的列电路的像素信号被采样和内插。 分级电路对来自不同传感器电路列线的模拟像素和复位信号进行采样。 一旦在合并电路中对预定数量的列线进行采样，则在一次操作中采样像素信号被平均化，而在另一操作中复位信号被平均化。

    Variable quantization ADC for image sensors
    16.
    发明申请
    Variable quantization ADC for image sensors 失效
    图像传感器的可变量化ADC

    公开(公告)号：US20070069936A1

    公开(公告)日：2007-03-29

    申请号：US11523097

    申请日：2006-09-19

    申请人： Alexander Krymski

    发明人： Alexander Krymski

    IPC分类号： H03M1/12

    CPC分类号： H03M1/367 ,  H03M1/56

    摘要： An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

    摘要翻译： 适用于其中噪声信号功率随着信号的信号功率（诸如成像系统）增加的系统中的A / D转换器利用可变量化系统将模拟信号转换为数字信号。 控制可变量化，使得在低信号电平下，量化与常规A / D转换器相似或相同，而量化电平在较高信号电平下增加。 因此，在低信号电平下提供更高的分辨率，而在高信号电平下产生较低的分辨率。

    Image sensors, methods, and pixels with tri-level biased transfer gates
    19.
    发明授权
    Image sensors, methods, and pixels with tri-level biased transfer gates 有权
    图像传感器，方法和具有三电平偏置传输门的像素

    公开(公告)号：US09369648B2

    公开(公告)日：2016-06-14

    申请号：US14061697

    申请日：2013-10-23

    申请人： Alexander Krymski

    发明人： Jaroslav Hynecek ,  Alexander Krymski

    IPC分类号： H04N5/335 ,  H04N5/3745 ,  H01L27/146

    CPC分类号： H04N5/37452 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14656 ,  H01L27/14689

    摘要： An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

    摘要翻译： 图像传感器包括至少一个具有传输门的像素，该传输门在至少三个偏置条件中是可控的，包括第一偏置条件，其中电子可以从光电二极管转移到传输门下面的势阱;第二偏置条件，其中 电子被限制在传输栅极下方的势阱中，以及第三偏置条件，其中电子可以在传输门下面的势阱中传输出去。 像素包括至少部分地位于传输栅极的一部分下方的p +型掺杂势垒注入，以及位于传输栅极与光电二极管相反侧的钉扎电荷转移势垒，该光栅包括p +型掺杂区域和n- 型掺杂区域。 图像传感器可以在全局快门模式和/或滚动快门模式下操作。

    CAMERAS AND METHODS WITH DATA PROCESSING, MEMORIES, AND AN IMAGE SENSOR WITH MULTIPLE DATA PORTS
    20.
    发明申请
    CAMERAS AND METHODS WITH DATA PROCESSING, MEMORIES, AND AN IMAGE SENSOR WITH MULTIPLE DATA PORTS 有权
    具有数据处理，存储器和具有多个数据端口的图像传感器的摄像机和方法

    公开(公告)号：US20150181148A1

    公开(公告)日：2015-06-25

    申请号：US14458151

    申请日：2014-08-12

    申请人： Alexander Krymski d.b.a. Alexima

    发明人： Alexey Slovick ,  Alexander Krymski

    IPC分类号： H04N5/3745 ,  H04N5/378 ,  H04N5/232

    CPC分类号： H04N5/378

    摘要： A camera includes a first processing device, a second processing device, and an image sensor that has a first plurality of ports connected to the first processing device and a second plurality of ports connected to the second processing device. A method includes providing first data from the first plurality of ports of the image sensor to the first processing device, and providing second data from the second plurality of ports of the image sensor to the second processing device. Another camera includes a first memory, a second memory, and an image sensor having a first plurality of ports connected to the first memory and a second plurality of ports connected to the second memory. A method includes providing first data from the first plurality of ports to the first memory and providing second data from the second plurality of ports to the second memory.

    摘要翻译： 相机包括第一处理装置，第二处理装置和具有连接到第一处理装置的第一多个端口和连接到第二处理装置的第二多个端口的图像传感器。 一种方法包括从图像传感器的第一多个端口向第一处理设备提供第一数据，以及从图像传感器的第二多个端口向第二处理设备提供第二数据。 另一相机包括第一存储器，第二存储器和具有连接到第一存储器的第一多个端口和连接到第二存储器的第二多个端口的图像传感器。 一种方法包括从第一多个端口向第一存储器提供第一数据，并将第二数据从第二多个端口提供给第二存储器。