公开(公告)号：US20240162915A1

公开(公告)日：2024-05-16

申请号：US18418957

申请日：2024-01-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Gavin MCVEIGH

IPC: H03M1/78 ,  G01L1/22 ,  H03M1/06 ,  H03M1/16 ,  H03M1/66 ,  H03M1/80

CPC classification number: H03M1/785 ,  G01L1/2268 ,  H03M1/0607 ,  H03M1/16 ,  H03M1/662 ,  H03M1/802 ,  H03F3/45

Abstract: The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

公开(公告)号：US11962277B2

公开(公告)日：2024-04-16

申请号：US17779823

申请日：2020-11-18

Applicant: ams International AG

Inventor： Fridolin Michel

IPC: H03M1/38 ,  G04F10/00 ,  H03F3/45 ,  H03M1/06

CPC classification number: H03F3/45179 ,  G04F10/005 ,  H03M1/0607 ,  H03F2200/78

Abstract: A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

公开(公告)号：US20230412187A1

公开(公告)日：2023-12-21

申请号：US18031188

申请日：2021-10-29

Applicant: Ciena Corporation

Inventor： Mohammad Honarparvar ,  Sadok Aouini ,  Jerry Yee-Tung Lam ,  Soheyl Ziabakhsh Shalmani ,  Naim Ben-Hamida

IPC: H03M1/66 ,  H03M1/20 ,  H03M1/06

CPC classification number: H03M1/661 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/20

Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

公开(公告)号：US20230299779A1

公开(公告)日：2023-09-21

申请号：US18096992

申请日：2023-01-13

Applicant: Infinera Corporation

Inventor： Shiva Prasad Kotagiri ,  Fu-Tai An

IPC: H03M1/06 ,  H04B10/60

CPC classification number: H03M1/0607 ,  H04B10/60

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing a SAR ADC circuit with improved quantization error. In some implementations, an apparatus includes an analog-to-digital converter (ADC) configured to receive a set of voltage signals and generate digital representations of signals. The ADC comprises a capacitive digital-to-analog converter (CDAC) comprising a capacitive divider circuit, the capacitive divider circuit comprising (i) a first capacitor in parallel with a second capacitor in a first branch, (ii) a plurality of capacitors in a plurality of other respective branches, and (iii) the CDAC configured to receive the set of sampled voltages and adjust each set of the sampled voltages by a first voltage or a second voltage through selection of one or more capacitors of the (i) first capacitor and the second capacitor and (ii) one or more of the plurality of capacitors.

公开(公告)号：US20190215001A1

公开(公告)日：2019-07-11

申请号：US15986084

申请日：2018-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun ZHANG

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M7/16

Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

公开(公告)号：US20190123751A1

公开(公告)日：2019-04-25

申请号：US16218334

申请日：2018-12-12

Applicant: Intel IP Corporation

Inventor： John G. Kauffman ,  Udo Schuetz

IPC: H03M1/06 ,  H03M1/10 ,  H03M3/00

CPC classification number: H03M1/06 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/1004 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/742 ,  H03M1/804 ,  H03M3/30 ,  H03M3/422 ,  H03M3/454 ,  H03M3/464

Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

公开(公告)号：US09960778B2

公开(公告)日：2018-05-01

申请号：US15472866

申请日：2017-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06

CPC classification number: H03M1/0607 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0629 ,  H01L2924/0002 ,  H03M1/0604 ,  H03M1/1023 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/442 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H01L2924/00

Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.

公开(公告)号：US20180069566A1

公开(公告)日：2018-03-08

申请号：US15466691

申请日：2017-03-22

Applicant: Texas Instruments Incorporated

Inventor： Rishi Soundararajan

IPC: H03M1/46 ,  H03K5/24 ,  H03M1/06

CPC classification number: H03M1/46 ,  H03K5/2481 ,  H03M1/0607 ,  H03M1/36 ,  H03M1/44 ,  H03M1/48

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

公开(公告)号：US20180063457A1

公开(公告)日：2018-03-01

申请号：US15251950

申请日：2016-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Nobutaka SHIMAMURA ,  Kazuhisa SUZUKI

IPC: H04N5/369 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H04N5/378 ,  H04N5/376

CPC classification number: H04N5/3698 ,  H03M1/002 ,  H03M1/0607 ,  H03M1/0639 ,  H03M1/12 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3577 ,  H04N5/3765 ,  H04N5/378

Abstract: Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

公开(公告)号：US20170359080A1

公开(公告)日：2017-12-14

申请号：US15633157

申请日：2017-06-26

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/68

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/68

Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.