Processor for multiple cache coherent protocols
    11.
    发明授权
    Processor for multiple cache coherent protocols 失效
    多高速缓存一致性协议的处理器

    公开(公告)号:US5301298A

    公开(公告)日:1994-04-05

    申请号:US775161

    申请日:1991-10-11

    IPC分类号: G06F12/08 G06F12/10 G06F13/14

    摘要: An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

    摘要翻译: 公开了允许选择回写,直写或一次写入协议的微处理器的改进。 引脚连接到接地或Vcc电位以选择直写或回写协议。 当该引脚连接到读/写线时,选择一次写入协议。 描述两个处理器之间的互连,其允许处理器以最小的胶合逻辑以一次写入协议操作。