公开(公告)号：US5301298A

公开(公告)日：1994-04-05

申请号：US775161

申请日：1991-10-11

申请人： Michael Kagan ,  Itamar Kazachinsky ,  Simcha Gochman ,  Tal Gat

发明人： Michael Kagan ,  Itamar Kazachinsky ,  Simcha Gochman ,  Tal Gat

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/14

CPC分类号： G06F12/0859 ,  G06F12/0815 ,  G06F12/0864 ,  G06F12/1045

摘要： An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

摘要翻译： 公开了允许选择回写，直写或一次写入协议的微处理器的改进。 引脚连接到接地或Vcc电位以选择直写或回写协议。 当该引脚连接到读/写线时，选择一次写入协议。 描述两个处理器之间的互连，其允许处理器以最小的胶合逻辑以一次写入协议操作。

公开(公告)号：US5379396A

公开(公告)日：1995-01-03

申请号：US777765

申请日：1991-10-11

申请人： Simcha Gochman ,  Itamar Kazachinsky ,  Michael Kagan

发明人： Simcha Gochman ,  Itamar Kazachinsky ,  Michael Kagan

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/16

CPC分类号： G06F12/0804 ,  G06F12/1045

摘要： An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

摘要翻译： 具有缓存存储器的微处理器的改进提供强而弱的写入顺序模式。 微处理器包括用于接收指示外部写入缓冲器是否为空的信号的端子和指示内部写入缓冲器是否为空的内部信号。 如果写入缓冲区不为空，并且在写入周期期间发生命中条件，直到缓冲区为空，微处理器的操作将以强排序模式停止。

公开(公告)号：US5367660A

公开(公告)日：1994-11-22

申请号：US241328

申请日：1994-05-11

申请人： Tal Gat ,  Simcha Gochman ,  Michael Kagan

发明人： Tal Gat ,  Simcha Gochman ,  Michael Kagan

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F12/0815 ,  G06F12/0859

摘要： An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

摘要翻译： 用于微处理器的改进的高速缓冲存储器。 使用存储标签和偏移字段的行缓冲器以及相应的数据行。 有效位与存储在行缓冲区中的不同数量的数据相关联。 因此，在行填充期间，作为示例，可以在从主存储器填充整行之前从行缓冲器读取指令。

公开(公告)号：US08645964B2

公开(公告)日：2014-02-04

申请号：US11208528

申请日：2005-08-23

申请人： Michael Kagan ,  Dror Goldenberg ,  Benny Koren ,  Michael Tsirkin

发明人： Michael Kagan ,  Dror Goldenberg ,  Benny Koren ,  Michael Tsirkin

IPC分类号： G06F9/46

CPC分类号： G06F9/45558 ,  G06F13/12

摘要： A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor.

摘要翻译： 一种用于加速虚拟机上的输入/输出（IO）访问操作的系统和方法，该方法包括提供包括不受限制的命令队列（CQ）和多个受限CQ的智能IO设备，并允许来宾域直接配置 并通过相应的限制CQ来控制IO资源，分配给访客域的IO资源。 在优选实施例中，IO资源到每个访客域的分配由特权虚拟交换元件执行。 在一些实施例中，智能IO设备是HCA，并且特权虚拟交换元件是管理程序。

公开(公告)号：US20130067193A1

公开(公告)日：2013-03-14

申请号：US13229772

申请日：2011-09-12

申请人： Michael Kagan ,  Ariel Shahar ,  Noam Bloch

发明人： Michael Kagan ,  Ariel Shahar ,  Noam Bloch

IPC分类号： G06F12/10

CPC分类号： G06F12/1081

摘要： An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

摘要翻译： 输入/输出（I / O）设备包括用于连接到具有存储器的主机设备的主机接口和网络接口，其被配置为通过网络发送和接收与指向的I / O操作相关联的数据分组 到内存中指定的虚拟地址。 处理电路被配置为使用结合I / O操作提供的存储器键将虚拟地址转换成物理地址，并且通过访问存储器中的物理地址来执行I / O操作。 存储键中的至少一个是间接存储器密钥，其指向对应于虚拟地址的多个相应范围的多个直接存储器密钥，使得引用间接存储器密钥的I / O操作可以使处理电路访问 在多个相应范围中的至少两个中的存储器。

公开(公告)号：US08255475B2

公开(公告)日：2012-08-28

申请号：US12430912

申请日：2009-04-28

申请人： Michael Kagan ,  Diego Crupnicoff ,  Dror Goldenberg ,  Liran Liss

发明人： Michael Kagan ,  Diego Crupnicoff ,  Dror Goldenberg ,  Liran Liss

IPC分类号： G06F15/167

CPC分类号： G06F12/1072 ,  G06F12/145

摘要： An input/output (I/O) device includes a host interface for connection to a host device having a memory and a network interface, which is configured to receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Packet processing hardware is configured to translate the virtual addresses into physical addresses and to perform the I/O operations using the physical addresses, and upon an occurrence of a page fault in translating one of the virtual addresses, to transmit a response packet over the network to a source of the data packets so as to cause the source to refrain from transmitting further data packets while the page fault is serviced.

摘要翻译： 输入/输出（I / O）设备包括用于连接到具有存储器和网络接口的主机设备的主机接口，其被配置为通过网络接收与指向虚拟的I / O操作相关联的数据分组 地址在内存中。 分组处理硬件被配置为将虚拟地址转换为物理地址并且使用物理地址执行I / O操作，并且在翻译虚拟地址之一时出现页面故障时，通过网络发送响应分组 到数据分组的源，以便在页面故障被维护时使得源不被发送进一步的数据分组。

公开(公告)号：US20120174102A1

公开(公告)日：2012-07-05

申请号：US13420641

申请日：2012-03-15

申请人： Michael Kagan ,  Dror Goldenberg ,  Benny Koren ,  Michael Tsirkin

发明人： Michael Kagan ,  Dror Goldenberg ,  Benny Koren ,  Michael Tsirkin

IPC分类号： G06F9/455

CPC分类号： G06F9/45558 ,  G06F13/12

摘要： A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor.

摘要翻译： 一种用于加速虚拟机上的输入/输出（IO）访问操作的系统和方法，该方法包括提供包括不受限制的命令队列（CQ）和多个受限CQ的智能IO设备，并允许来宾域直接配置 并通过相应的限制CQ来控制IO资源，分配给访客域的IO资源。 在优选实施例中，IO资源到每个访客域的分配由特权虚拟交换元件执行。 在一些实施例中，智能IO设备是HCA，并且特权虚拟交换元件是管理程序。

公开(公告)号：US08051212B2

公开(公告)日：2011-11-01

申请号：US10000456

申请日：2001-12-04

申请人： Michael Kagan ,  Diego Crupnicoff ,  Margarita Shnitman ,  Ariel Shachar ,  Ram Izhaki ,  Gilad Shainer ,  Aviram Gutman ,  Benny Koren ,  Dafna Levenvirth ,  Gil Bloch ,  Yael Shenhav

发明人： Michael Kagan ,  Diego Crupnicoff ,  Margarita Shnitman ,  Ariel Shachar ,  Ram Izhaki ,  Gilad Shainer ,  Aviram Gutman ,  Benny Koren ,  Dafna Levenvirth ,  Gil Bloch ,  Yael Shenhav

IPC分类号： G06F15/16

CPC分类号： G06F13/1605 ,  H04L49/90

摘要： A network interface adapter includes an outgoing packet generator, adapted to generate an outgoing request packet for delivery to a remote responder responsive to a request submitted by a host processor and a network output port, coupled to transmit the outgoing request packet over a network to the remote responder. A network input port receives an incoming response packet from the remote responder, in response to the outgoing request packet sent thereto, as well as an incoming request packet sent by a remote requester. An incoming packet processor receives and processes both the incoming response packet and the incoming request packet, and causes the outgoing packet generator, responsive to the incoming request packet, to generate, in addition to the outgoing request packet, an outgoing response packet for transmission to the remote requester.

摘要翻译： 网络接口适配器包括输出分组生成器，其适于响应于由主处理器和网络输出端口提交的请求而生成用于传送到远程响应者的输出请求分组，所述请求被耦合以通过网络将所述输出请求分组传送到 远程响应者。 网络输入端口响应于向其发送的传出请求分组以及由远程请求者发送的传入请求分组，从远程应答器接收传入响应分组。 输入分组处理器接收并处理输入响应分组和传入请求分组，并且响应于传入请求分组使输出分组生成器除了输出请求分组之外还生成用于传输的输出响应分组 远程请求者。

公开(公告)号：US20110083064A1

公开(公告)日：2011-04-07

申请号：US12573119

申请日：2009-10-04

申请人： Michael Kagan ,  Noam Bloch ,  Ariel Shachar

发明人： Michael Kagan ,  Noam Bloch ,  Ariel Shachar

IPC分类号： G06F11/07 ,  G06F15/16

CPC分类号： H04L67/1097 ,  H04L63/123

摘要： A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.

摘要翻译： 网络通信设备包括主机接口，其被耦合以与主机处理器通信，具有主机存储器，以便接收工作请求以执行要通过分组网络传送多个数据块的事务 。 处理电路被配置为处理多个数据分组以执行事务，事务中的每个数据分组包含一部分数据块，并且多个数据分组至少包括第一和最后一个分组，其分别包含第一和最后一个分组 数据块的交易。 处理电路被配置为在处理数据分组时计算数据块上的事务签名，使得至少第一数据块在完成交易签名的计算之前通过其中一个接口通过网络通信设备。

公开(公告)号：US20110010557A1

公开(公告)日：2011-01-13

申请号：US12498381

申请日：2009-07-07

申请人： Michael Kagan ,  Noam Bloch

发明人： Michael Kagan ,  Noam Bloch

IPC分类号： H04L9/32 ,  G06F3/00

CPC分类号： H04L9/3247 ,  H04L2209/80

摘要： A method of controlling a peripheral device includes generating, in a host processor, a control message for transmission to the peripheral device, and calculating a signature for the control message. The control message and the signature are written to an address in a system memory of the host processor, and the peripheral device is notified of the address, so as to cause the device to read the control message and the signature from the system memory.

摘要翻译： 一种控制外围设备的方法包括在主处理器中生成用于传输到外围设备的控制消息，以及计算控制消息的签名。 将控制消息和签名写入主处理器的系统存储器中的地址，并向外围设备通知地址，以使设备从系统存储器读取控制消息和签名。