公开(公告)号：US10700564B2

公开(公告)日：2020-06-30

申请号：US15489443

申请日：2017-04-17

Applicant: General Electric Company

Inventor： Christopher Michael Calebrese ,  Jeffrey S. Sullivan ,  Qin Chen ,  Benjamin Hale Winkler ,  Kevin Warner Flanagan ,  Anil Raj Duggal

IPC: H02K15/00 ,  H02K3/12 ,  H02K3/24 ,  H02K3/40 ,  H02K3/30 ,  H02K3/34

Abstract: A method includes forming one or more cores, wherein each of the one or more cores has a cross section corresponding to a conductor to be subsequently formed, forming an insulator around the one or more cores, removing the one or more cores to expose one or more recesses within the insulator, and forming one or more conductors in at least one of the one or more recesses of the insulator such that the cross sections of the one or more conductors conform to an interior surface of the one or more recesses in the insulator.

公开(公告)号：US10333374B2

公开(公告)日：2019-06-25

申请号：US15589422

申请日：2017-05-08

Applicant: General Electric Company

Inventor： Jeffrey Stuart Sullivan ,  Christopher Michael Calebrese ,  Qin Chen ,  Alexander Rene Anderton ,  Massimiliano Vezzoli

IPC: H02K3/30 ,  H02K3/34 ,  H02K3/40 ,  H01B19/04 ,  H02K15/10 ,  H02P27/08

Abstract: Insulation systems that present an electrical stress grading through the disposition of resistively graded networks between insulating layers is described. The resistively graded networks may be implemented by coating insulating material with resistive material, and wrapping the insulation material around a conductor. The resistive material may be linear or non-linear material. Fabrication of the insulating material, the resistive material, and the coating process are also discussed, as well as the application of the insulation to the conductor are also discussed.