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公开(公告)号：US10754654B2
公开(公告)日：2020-08-25
申请号：US16368288
申请日：2019-03-28
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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公开(公告)号：US10685422B2
公开(公告)日：2020-06-16
申请号：US16272819
申请日：2019-02-11
Applicant: Google LLC
Inventor： Albert Meixner , Hyunchul Park , Qiuling Zhu , Jason Rupert Redgrave
Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
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公开(公告)号：US20200120287A1
公开(公告)日：2020-04-16
申请号：US16659702
申请日：2019-10-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
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公开(公告)号：US20190220282A1
公开(公告)日：2019-07-18
申请号：US16368288
申请日：2019-03-28
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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公开(公告)号：US11153464B2
公开(公告)日：2021-10-19
申请号：US16526063
申请日：2019-07-30
Applicant: Google LLC
Inventor： Ofer Shacham , Jason Rupert Redgrave , Albert Meixner , Qiuling Zhu , Daniel Frederic Finchelstein , David Patterson , Donald Stark
Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
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Patent Agency Ranking
公开(公告)号：US11140293B2
公开(公告)日：2021-10-05
申请号：US16786359
申请日：2020-02-10
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
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公开(公告)号：US10719905B2
公开(公告)日：2020-07-21
申请号：US16547801
申请日：2019-08-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US10417732B2
公开(公告)日：2019-09-17
申请号：US15599348
申请日：2017-05-18
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US20190188824A1
公开(公告)日：2019-06-20
申请号：US16272819
申请日：2019-02-11
Applicant: Google LLC
Inventor： Albert Meixner , Hyunchul Park , Qiuling Zhu , Jason Rupert Redgrave
Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
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公开(公告)号：US10304156B2
公开(公告)日：2019-05-28
申请号：US15625972
申请日：2017-06-16
Applicant: Google LLC
Inventor： Albert Meixner , Hyunchul Park , Qiuling Zhu , Jason Rupert Redgrave
Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
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