公开(公告)号：US10267858B2

公开(公告)日：2019-04-23

申请号：US15482336

申请日：2017-04-07

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen

IPC: G01R31/3185 ,  G06F11/25 ,  G01R31/317 ,  G06F21/85

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

公开(公告)号：US11429069B2

公开(公告)日：2022-08-30

申请号：US16715948

申请日：2019-12-16

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson ,  Joshua Robert Dunning

IPC: G05B13/02 ,  G06N3/08 ,  G06N3/04

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

公开(公告)号：US11231296B2

公开(公告)日：2022-01-25

申请号：US15131706

申请日：2016-04-18

Applicant: Hamilton Sundstrand Corporation

Inventor： Gary L. Hess ,  Kanwalpreet Reen

IPC: G01D5/22 ,  G01D5/20

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the primary winding, and an analog-to-digital converter electrically connected to the secondary winding. A control module is operatively connected to analog-to-digital converter and is responsive to instructions to apply an excitation voltage with an oscillating waveform to the primary winding, induce a secondary voltage using the secondary winding using the excitation voltage, and acquire a plurality of voltage measurements from the secondary winding separated by a time interval corresponding to π/3 of the excitation voltage oscillating waveform.

公开(公告)号：US20210181694A1

公开(公告)日：2021-06-17

申请号：US16715948

申请日：2019-12-16

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson ,  Joshua Robert Dunning

IPC: G05B13/02 ,  G06N3/04 ,  G06N3/08

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

公开(公告)号：US20190278633A1

公开(公告)日：2019-09-12

申请号：US15914121

申请日：2018-03-07

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen

IPC: G06F9/52 ,  G01R31/00

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

公开(公告)号：US20180292458A1

公开(公告)日：2018-10-11

申请号：US15482336

申请日：2017-04-07

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen

IPC: G01R31/3185 ,  G06F11/25

CPC classification number: G01R31/318597 ,  G01R31/31719 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318588 ,  G06F11/25 ,  G06F21/85

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.