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    System on chip for performing scan test and method of designing the same
    2.
    发明授权
    System on chip for performing scan test and method of designing the same 有权

    公开(公告)号：US11940494B2

    公开(公告)日：2024-03-26

    申请号：US17859870

    申请日：2022-07-07

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Woohyun Son ,  Kiseok Bae

    IPC分类号： G06F30/333 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3193

    CPC分类号： G01R31/318597 ,  G01R31/31719 ,  G01R31/31727 ,  G01R31/31935

    摘要： A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

    DDR5 SDRAM DIMM SLOT DETECTION SYSTEM AND METHOD THEREOF
    3.
    发明公开
    DDR5 SDRAM DIMM SLOT DETECTION SYSTEM AND METHOD THEREOF 审中-公开

    公开(公告)号：US20230296673A1

    公开(公告)日：2023-09-21

    申请号：US17701429

    申请日：2022-03-22

    申请人： Inventec (Pudong) Technology Corporation ,  Inventec Corporation

    发明人： Jin-Dong Zhao

    IPC分类号： G01R31/319 ,  G01R31/3185

    CPC分类号： G01R31/31905 ,  G01R31/318597 ,  G01R31/318572

    摘要： A DDR5 SDRAM DIMM slot detection system and a method thereof are disclosed. A first detection board is serially connected to a second detection board, a JTAG controller converts a DIMM detection instruction, which is generated by a detection device, into a DIMM detection instruction in JTAG format; the DIMM detection instruction in JTAG format is provided to the first detection board or second detection board through the adapter circuit board, so as to detect DDR5 SDRAM DIMM slots of the circuit board under test, thereby achieving the technical effect of improving efficiency in detection for DDR5 SDRAM DIMM connection interface.

    COMMANDED JTAG TEST ACCESS PORT OPERATIONS
    5.
    发明公开
    COMMANDED JTAG TEST ACCESS PORT OPERATIONS 审中-公开

    公开(公告)号：US20230221368A1

    公开(公告)日：2023-07-13

    申请号：US18120582

    申请日：2023-03-13

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318597 ,  G01R31/318552 ,  G01R31/318572

    摘要： The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

    SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME
    6.
    发明公开
    SYSTEM ON CHIP FOR PERFORMING SCAN TEST AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20230141786A1

    公开(公告)日：2023-05-11

    申请号：US17859870

    申请日：2022-07-07

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： WOOHYUN SON ,  KISEOK BAE

    IPC分类号： G01R31/3185 ,  G01R31/3193 ,  G01R31/317

    CPC分类号： G01R31/318597 ,  G01R31/31935 ,  G01R31/31719 ,  G01R31/31727

    摘要： A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

    SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE
    8.
    发明申请
    SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE 审中-公开

    公开(公告)号：US20190064271A1

    公开(公告)日：2019-02-28

    申请号：US15684334

    申请日：2017-08-23

    申请人： STMicroelectronics International N.V.

    发明人： Venkata Narayanan Srinivasan ,  Manish Sharma

    IPC分类号： G01R31/3185 ,  G01R31/317

    CPC分类号： G01R31/31705 ,  G01R31/318597

    摘要： A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.