公开(公告)号：US08429214B2

公开(公告)日：2013-04-23

申请号：US12885103

申请日：2010-09-17

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US20110010406A1

公开(公告)日：2011-01-13

申请号：US12885103

申请日：2010-09-17

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US07814136B1

公开(公告)日：2010-10-12

申请号：US11344694

申请日：2006-02-01

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US06980029B1

公开(公告)日：2005-12-27

申请号：US10319720

申请日：2002-12-13

申请人： Ashok Vittal ,  Hare K. Verma

发明人： Ashok Vittal ,  Hare K. Verma

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.

摘要翻译： 可编程逻辑器件具有多个级别的具有固定互连的可编程逻辑模块。 电平的输出连接到下一级可编程逻辑模块的输入。 第一级从存储器元件组馈送，并且存储元件组的输入从最后一级派生。 交叉开关可选地插入精心挑选的水平对之间。

公开(公告)号：US07417455B2

公开(公告)日：2008-08-26

申请号：US11128575

申请日：2005-05-14

申请人： Hare K. Verma ,  Ashok Vittal

发明人： Hare K. Verma ,  Ashok Vittal

IPC分类号： H03K19/177

CPC分类号： H03K19/1733

摘要： A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

摘要翻译： 描述了可以被配置为组合逻辑，顺序逻辑或路由单元的函数发生器。 功能发生器耦合到从多个输入中选择导线的多个选择器块。 选定的导线是函数发生器的输入。 当配置为组合逻辑单元时，函数发生器可以生成其输入的任何函数。 函数发生器配置为顺序逻辑单元时，作为一个寄存器，其中任何一个输入都可以被指向输入数据，清零，时钟使能或复位信号。 寄存器可配置为下降沿或上升沿触发器或正或负电平敏感锁存器。 作为路由元件，逻辑单元选择其输入之一。 可编程单元的输出可以扇出到另一个集成单元的一个或多个输入。

公开(公告)号：US20090160483A1

公开(公告)日：2009-06-25

申请号：US12315653

申请日：2008-12-05

申请人： Hare K. Verma ,  Manoj Gunwani ,  Conrad Kong ,  Jai Liu ,  Nilanjan Chatterjee

发明人： Hare K. Verma ,  Manoj Gunwani ,  Conrad Kong ,  Jai Liu ,  Nilanjan Chatterjee

IPC分类号： H03K19/177 ,  G06F17/50

CPC分类号： H03K19/177

摘要： A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.

摘要翻译： 提供了一种用于现场可编程专用集成电路（ASIC）实现的可编程逻辑阵列。 可编程逻辑阵列包括可编程逻辑块和可编程逻辑接口。 可编程逻辑接口将可编程逻辑块耦合到现场可编程ASIC的外部接口，并使可编程逻辑阵列作为硬宏块插入现场可编程ASIC。

公开(公告)号：US20110058431A1

公开(公告)日：2011-03-10

申请号：US12554747

申请日：2009-09-04

申请人： Manoj Gunwani ,  Hare K. Verma ,  Cordell Prater

发明人： Manoj Gunwani ,  Hare K. Verma ,  Cordell Prater

IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K19/177

CPC分类号： G11C29/40 ,  G11C2029/0401 ,  H03K19/17748 ,  H03K19/1776

摘要： A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value. For example, in some embodiments the mode value indicates one of four patterns, a normal pattern, a block checkerboard pattern, a bank checkerboard pattern, and an all banks pattern.

摘要翻译： 公开了可以与现场可编程门阵列一起使用的存储器。 在一些实施例中，存储器可以包括包括多个存储体的存储器阵列，每个存储体包括至少一个存储器块，所述至少一个存储器块中的每一个包括存储器单元阵列; 耦合到所述至少一个存储器块中的每一个的地址解码器，所述地址解码器包括耦合以接收输入地址和块地址的比较器，并且提供指示输入地址的一部分何时与块地址匹配的比较位;以及 或门，其耦合以接收所述比较位和通配符位，当所述比较位或所述通配符位被置位时，所述或门向所述存储器块提供使能; 以及接收模式值和输入地址并将通配符位提供给每个地址解码器的逻辑单元。 可以根据模式值将数据同时写入存储器阵列。 例如，在一些实施例中，模式值指示四种图案之一，正常图案，块棋盘格图案，银行棋盘图案和全部银行图案。

公开(公告)号：US06317768B1

公开(公告)日：2001-11-13

申请号：US09670488

申请日：2000-09-26

申请人： Hare K. Verma ,  Sudip K. Nag

发明人： Hare K. Verma ,  Sudip K. Nag

IPC分类号： G06F1500

CPC分类号： G06F17/142

摘要： A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

摘要翻译： 公开了一种用于在包括多个RADIX-2元件的电路中提供高度并行的FFT计算的系统和方法。 分区RAM资源允许所有阶段的RADIX都具有最佳的带宽内存访问。 优选地，对于早期RADIX阶段和“关键”阶段，更多的存储器可用。 在关键阶段之外的RADIX优选地每个仅需要一个RAM分区，因此可以在不影响存储器资源的情况下同时操作。 在具有P RAM分区和P RADIX阶段的优选配置中，关键阶段是阶段编号log2P，直到关键阶段，只有P / 2 RADIX单元可以在每个阶段内同时运行。 在关键阶段之后，每个阶段的所有RADIX都可以同时运行。

公开(公告)号：US06911842B1

公开(公告)日：2005-06-28

申请号：US10090239

申请日：2002-03-01

申请人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

发明人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K17/693 ,  H03K19/173 ,  H03K19/77

CPC分类号： G06F1/10

摘要： A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.

摘要翻译： 提供了支持多千兆位收发器（MGT）的可编程逻辑器件（PLD）。 PLD包括用于接收一个或多个高质量差分时钟信号的一对或多对共享时钟焊盘。 专用时钟跟踪将每对共享时钟接口耦合到PLD上的一个或多个MGT。 每个MGT包括时钟多路复用器电路，其允许将高质量差分时钟信号中的一个作为MGT的参考时钟信号进行路由。 时钟多路复用器电路被设计成使得高质量时钟信号不会增加显着的抖动。 时钟多路复用器电路还可以将由PLD接收的通用时钟信号作为MGT的较低质量参考时钟信号。 可以降低由时钟多路复用器电路路由的参考时钟信号，为MGT的物理编码子层提供参考时钟。

公开(公告)号：US07111220B1

公开(公告)日：2006-09-19

申请号：US10090519

申请日：2002-03-01

申请人： Paul T. Sasaki ,  Suresh M. Menon ,  Atul V. Ghia ,  Warren E. Cory ,  Hare K. Verma ,  Philip M. Freidin

发明人： Paul T. Sasaki ,  Suresh M. Menon ,  Atul V. Ghia ,  Warren E. Cory ,  Hare K. Verma ,  Philip M. Freidin

IPC分类号： H03M13/00

CPC分类号： H03M13/091 ,  H03M13/6519 ,  H04L69/32 ,  H04L69/324

摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

摘要翻译： 公开了用于准备通过网络传输的数据的方法和结构。 在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。 物理层的CRC生成器符合多个网络通信标准。