公开(公告)号：US20200242189A1

公开(公告)日：2020-07-30

申请号：US16260331

申请日：2019-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Soumitra Chatterjee ,  Sunil Vishwanathpur Lakshminarasimha ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06N3/04 ,  G06F8/20 ,  G06F9/44

Abstract: In an example, a neural network program corresponding to a neural network model is received. The neural network program includes matrices, vectors, and matrix-vector multiplication (MVM) operations. A computation graph corresponding to the neural network model is generated. The computation graph includes a plurality of nodes, each node representing a MVM operation, a matrix, or a vector. Further, a class model corresponding to the neural network model is populated with a data structure pointing to the computation graph. The computation graph is traversed based on the class model. Based on the traversal, the plurality of MVM operations are assigned to MVM units of a neural network accelerator. Each MVM unit can perform a MVM operation. Based on assignment of the plurality of MVM operations, an executable file is generated for execution by the neural network accelerator.

公开(公告)号：US10726096B2

公开(公告)日：2020-07-28

申请号：US16159578

申请日：2018-10-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Soumitra Chatterjee ,  Chinmay Ghosh ,  Mashood Abdulla Kodavanji ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06N3/04 ,  G06N3/08

Abstract: Systems and methods are provided for sparse matrix vector multiplication with a matrix vector multiplication unit. The method includes partitioning a sparse matrix of entries into a plurality of sub-matrices; mapping each of the sub-matrices to one of a plurality of respective matrix vector multiplication engines; partitioning an input vector into a plurality of sub-vectors; computing, via each matrix vector multiplication engine, a plurality of intermediate result vectors each resulting from a multiplication of one of the sub-matrices and one of the sub-vectors; for each set of rows of the sparse matrix, adding elementwise the intermediate result vectors to produce a plurality of result sub-vectors; and concatenating the result sub-vectors to form a result vector.

公开(公告)号：US20200159810A1

公开(公告)日：2020-05-21

申请号：US16191767

申请日：2018-11-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Chinmay Ghosh ,  Soumitra Chatterjee ,  Mashood Abdulla Kodavanji ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06F9/50 ,  G06F9/30 ,  G06F9/38

Abstract: Example implementations relate to domain specific programming language (DSL) compiler for large scale sparse matrices. A method can comprise partitioning a sparse matrix into a plurality of submatrices based on a sparse matrix representation and inputting each one of the submatrices into a respective one of a plurality of matrix-vector multiplication units (MVMUs) of a crossbar-based architecture.