公开(公告)号：US11496492B2

公开(公告)日：2022-11-08

申请号：US16540969

申请日：2019-08-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Unum Sarfraz ,  Mohan Parthasarathy ,  Brijesh Nambiar ,  Min-Yi Shen ,  Viswesh Ananthakrishnan

IPC: G06F21/00 ,  H04L9/40

Abstract: Systems and methods are provided for managing false positives in a network anomaly detection system. The methods may include receiving a plurality of anomaly reports; extracting fields, and values for the fields, from each of the anomaly reports; grouping the anomaly reports into a plurality of groups according to association rule learning, wherein each group is defined by a respective rule; for each group, creating a cluster based on common values for the fields; and marking each cluster as a possible false positive anomaly cluster.

公开(公告)号：US11269973B2

公开(公告)日：2022-03-08

申请号：US16860357

申请日：2020-04-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mashood Abdulla Kodavanji ,  Soumitra Chatterjee ,  Chinmay Ghosh ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G11C13/00 ,  G06F16/22 ,  G06K9/62

Abstract: Repeating patterns are identified in a matrix. Based on the identification of the repeating patterns, instructions are generated, which are executable by processing cores of a dot product engine to allocate analog multiplication crossbars of the dot product engine to perform multiplication of the matrix with a vector.

公开(公告)号：US11132423B2

公开(公告)日：2021-09-28

申请号：US16176848

申请日：2018-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Soumitra Chatterjee ,  Mashood Abdulla K ,  Chinmay Ghosh ,  Mohan Parthasarathy

IPC: G06F17/16 ,  H03K19/177 ,  G06F9/30

Abstract: According to examples, an apparatus may include a processor and a non-transitory computer readable medium having instructions that when executed by the processor, may cause the processor to partition a matrix of elements into a plurality of sub-matrices of elements. Each sub-matrix of the plurality of sub-matrices may include elements from a set of columns of the matrix of elements that includes a nonzero element. The processor may also assign elements of the plurality of sub-matrices to a plurality of crossbar devices to maximize a number of nonzero elements of the matrix of elements assigned to the crossbar devices.

公开(公告)号：US20210232472A1

公开(公告)日：2021-07-29

申请号：US16773390

申请日：2020-01-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Venkatesh Nagaraj ,  Mohan Parthasarathy

IPC: G06F11/30 ,  G06F9/48 ,  G06F9/50 ,  G06N20/00 ,  G06K9/62 ,  H04L12/26 ,  H04L12/28

Abstract: Systems and methods described herein reduce latency between the time at which telemetry data is collected in data center and the time at which a remedial action is triggered to address an event that can be predicted based on the telemetry data. Telemetry data is collected in a data center and used to create training data for a machine-learning model configured to predict events in the data center based on patterns in the telemetry data. The machine-learning model is stored at an edge appliance in the data center. Incoming telemetry data can be converted into an input instance that is input into the machine learning model. The machine-learning model generates an output score for the input instance. The output score provides information that indicates whether a remedial action should be taken in the data center to achieve a desired outcome. If a remedial action should be taken, the edge device sends a signal to trigger the remedial action within the data center.

公开(公告)号：US11799714B2

公开(公告)日：2023-10-24

申请号：US17652335

申请日：2022-02-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mohan Parthasarathy ,  Matthew James Muggeridge ,  Vinay Venugopal ,  Srinivasan Varadarajan Sahasranamam

IPC: H04L41/04 ,  G06F9/48

CPC classification number: H04L41/04 ,  G06F9/48

Abstract: In some examples, a system includes a plurality of electronic devices each comprising a respective management processor and a baseboard management controller (BMC). A management processor of a cluster of management processors is a primary management processor to act as a management controller for the plurality of electronic devices. The management controller interacts with the BMC in a respective electronic device to perform management of the respective electronic device. The cluster of management processors performs failover responsive to a fault of the primary management processor to select another management processor of the cluster of the management processors as the management controller.

公开(公告)号：US11645358B2

公开(公告)日：2023-05-09

申请号：US16260331

申请日：2019-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Soumitra Chatterjee ,  Sunil Vishwanathpur Lakshminarasimha ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06F9/44 ,  G06F8/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/02

CPC classification number: G06F17/16 ,  G06F8/20 ,  G06F9/44 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, a neural network program corresponding to a neural network model is received. The neural network program includes matrices, vectors, and matrix-vector multiplication (MVM) operations. A computation graph corresponding to the neural network model is generated. The computation graph includes a plurality of nodes, each node representing a MVM operation, a matrix, or a vector. Further, a class model corresponding to the neural network model is populated with a data structure pointing to the computation graph. The computation graph is traversed based on the class model. Based on the traversal, the plurality of MVM operations are assigned to MVM units of a neural network accelerator. Each MVM unit can perform a MVM operation. Based on assignment of the plurality of MVM operations, an executable file is generated for execution by the neural network accelerator.

公开(公告)号：US11361050B2

公开(公告)日：2022-06-14

申请号：US16196423

申请日：2018-11-20

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Soumitra Chatterjee ,  Sunil Vishwanathpur Lakshminarasimha ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06N3/10 ,  G06F8/41

Abstract: Example implementations relate to assigning dependent matrix-vector multiplication (MVM) operations to consecutive crossbars of a dot product engine (DPE). A method can comprise grouping a first MVM operation of a computation graph with a second MVM operation of the computation graph where the first MVM operation is dependent on a result of the second MVM operation, assigning a first crossbar of a DPE to an operand of the first MVM operation, and assigning a second crossbar of the DPE to an operand of the second MVM operation, wherein the first and second crossbars are consecutive.

公开(公告)号：US20200242189A1

公开(公告)日：2020-07-30

申请号：US16260331

申请日：2019-01-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Soumitra Chatterjee ,  Sunil Vishwanathpur Lakshminarasimha ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06N3/04 ,  G06F8/20 ,  G06F9/44

Abstract: In an example, a neural network program corresponding to a neural network model is received. The neural network program includes matrices, vectors, and matrix-vector multiplication (MVM) operations. A computation graph corresponding to the neural network model is generated. The computation graph includes a plurality of nodes, each node representing a MVM operation, a matrix, or a vector. Further, a class model corresponding to the neural network model is populated with a data structure pointing to the computation graph. The computation graph is traversed based on the class model. Based on the traversal, the plurality of MVM operations are assigned to MVM units of a neural network accelerator. Each MVM unit can perform a MVM operation. Based on assignment of the plurality of MVM operations, an executable file is generated for execution by the neural network accelerator.

公开(公告)号：US10726096B2

公开(公告)日：2020-07-28

申请号：US16159578

申请日：2018-10-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Soumitra Chatterjee ,  Chinmay Ghosh ,  Mashood Abdulla Kodavanji ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06N3/04 ,  G06N3/08

Abstract: Systems and methods are provided for sparse matrix vector multiplication with a matrix vector multiplication unit. The method includes partitioning a sparse matrix of entries into a plurality of sub-matrices; mapping each of the sub-matrices to one of a plurality of respective matrix vector multiplication engines; partitioning an input vector into a plurality of sub-vectors; computing, via each matrix vector multiplication engine, a plurality of intermediate result vectors each resulting from a multiplication of one of the sub-matrices and one of the sub-vectors; for each set of rows of the sparse matrix, adding elementwise the intermediate result vectors to produce a plurality of result sub-vectors; and concatenating the result sub-vectors to form a result vector.

公开(公告)号：US20200159810A1

公开(公告)日：2020-05-21

申请号：US16191767

申请日：2018-11-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Chinmay Ghosh ,  Soumitra Chatterjee ,  Mashood Abdulla Kodavanji ,  Mohan Parthasarathy

IPC: G06F17/16 ,  G06F9/50 ,  G06F9/30 ,  G06F9/38

Abstract: Example implementations relate to domain specific programming language (DSL) compiler for large scale sparse matrices. A method can comprise partitioning a sparse matrix into a plurality of submatrices based on a sparse matrix representation and inputting each one of the submatrices into a respective one of a plurality of matrix-vector multiplication units (MVMUs) of a crossbar-based architecture.