公开(公告)号：US20170188996A1

公开(公告)日：2017-07-06

申请号：US15313147

申请日：2014-06-13

Applicant: HITACHI, LTD.

Inventor： Shinya KAJIYAMA ,  Yutaka IGARASHI ,  Toru YAZAKI

IPC: A61B8/00 ,  H03K17/10 ,  H03K3/012 ,  A61B8/08

Abstract: A transmit receive switch circuit has a first MOSFET (MN1) and a second MOSFET (MN2), goes into a switch-off state at the time of transmission, and goes into a switch-on state at the time of reception. The first MOSFET (MN1) and the second MOSFET (MN2) are connected between an input terminal (SWIN) and an output terminal (SWOUT). The switch circuit includes a shunt circuit (SHNT) that is connected between a common gate (COMG) and a common source (COMS), the common gate being connected to the gates of the first and second MOSFETs, and the common source being connected to the sources of the first and second MOSFETs. When a signal having a negative voltage relative to a reference voltage is applied to the input terminal, a switch that temporarily turns on causes the shunt circuit to short-circuit the common gate and the common source.

公开(公告)号：US20160363657A1

公开(公告)日：2016-12-15

申请号：US15121418

申请日：2014-02-26

Applicant: HITACHI, LTD.

Inventor： Tatsuo NAKAGAWA ,  Hiroshi MASUZAWA ,  Shinya KAJIYAMA

IPC: G01S7/52 ,  A61B8/14 ,  A61B8/00 ,  G01S15/89

CPC classification number: G01S7/52046 ,  A61B8/145 ,  A61B8/4444 ,  A61B8/4494 ,  A61B8/5207 ,  G01S7/52025 ,  G01S7/5208 ,  G01S15/8915 ,  G10K11/346

Abstract: A compact delay circuit that can dynamically change delay time is configured. A probe includes an analog memory unit that accumulates electric charges corresponding to a reflected wave of an ultrasonic wave produced by a difference between the acoustic impedances on a plurality of capacitors 303 and in turn outputs the electric charges accumulated on the capacitors 303 to an analog memory unit 205. In accumulating electric charges, when a control signal Ctls_l that increases delay time of the reflected wave is inputted, the analog memory unit 205 accumulates the same electric charges on two or more of the capacitors 303 for a preset period, or in outputting electric charges, when a control signal Ctlo_l is inputted, the analog memory unit 205 outputs the electric charges accumulated on one of the capacitors 303 for a preset period.

Abstract translation: 配置可以动态更改延迟时间的紧凑型延迟电路。 探头包括模拟存储器单元，其累积与由多个电容器303上的声阻抗之间的差产生的超声波的反射波相对应的电荷，然后将累积在电容器303上的电荷输出到模拟存储器 单元205.在累积电荷中，当输入增加反射波的延迟时间的控制信号Ctls_1时，模拟存储单元205在预定时段内在两个或更多个电容器303上累积相同的电荷，或者在输出 电荷，当输入控制信号Ctlo_1时，模拟存储单元205输出累积在一个电容器303上的预定时段的电荷。