公开(公告)号：US20120021578A1

公开(公告)日：2012-01-26

申请号：US13244455

申请日：2011-09-24

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

摘要翻译： 提供高性能的沟槽栅型功率晶体管。 作为栅电极的沟槽栅极形成为包括漏极层和外延层的超结结构。 在这种情况下，栅电极形成为使得外延层的上表面高于在漏极层上形成的沟道层的上表面。 然后，在沟道层和外延层的每一个上形成绝缘膜，然后去除绝缘膜的一部分，以在外延层的侧壁上形成侧壁间隔物。 随后，以侧壁间隔物作为掩模，去除沟道层的一部分和漏极层的一部分，以形成用于沟槽栅的沟槽。

公开(公告)号：US08030704B2

公开(公告)日：2011-10-04

申请号：US12434655

申请日：2009-05-03

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

摘要翻译： 提供高性能的沟槽栅型功率晶体管。 作为栅电极的沟槽栅极形成为包括漏极层和外延层的超结结构。 在这种情况下，栅电极形成为使得外延层的上表面高于在漏极层上形成的沟道层的上表面。 然后，在沟道层和外延层的每一个上形成绝缘膜，然后去除绝缘膜的一部分，以在外延层的侧壁上形成侧壁间隔物。 随后，以侧壁间隔物作为掩模，去除沟道层的一部分和漏极层的一部分，以形成用于沟槽栅的沟槽。

公开(公告)号：US07999345B2

公开(公告)日：2011-08-16

申请号：US12400436

申请日：2009-03-09

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L29/47

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806

摘要： Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

摘要翻译： 提供了一种在一个半导体衬底上具有功率MISFET和肖特基势垒二极管的半导体器件中的技术，其能够抑制功率MISFET的导通电阻的急剧增加，同时使肖特基势垒二极管的雪崩击穿电压更大 比功率MISFET。 在本发明中，在半导体衬底上形成两个外延层，一个具有高掺杂浓度且另一个具有低掺杂浓度的外延层，并且这两个外延层之间的边界位于相同深度或更浅的区域 沟槽的底部。

公开(公告)号：US08633510B2

公开(公告)日：2014-01-21

申请号：US13470473

申请日：2012-05-14

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66348

摘要： The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction.

摘要翻译： 本申请的发明提供了一种IE型沟槽IGBT。 在IE型沟槽IGBT中，构成单元区域的线性单元单元区域中的每一个主要由线性有源和非活动单元区域组成。 线性有源电池区域被分成具有发射极区域和在其纵向方向上看到的非活性部分的有源部分。

公开(公告)号：US08471333B2

公开(公告)日：2013-06-25

申请号：US13540586

申请日：2012-07-02

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L27/06

CPC分类号： H01L21/823487 ,  H01L27/0629

摘要： A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

摘要翻译： 形成沟槽以便从源极区域的上表面到达p型外延层。 形成栅电极以埋入沟槽。 每个主体接触沟槽远离栅电极形成。 身体接触区域形成在身体接触沟槽的底部。 作为本发明的特征的n型半导体区域形成在每个体接触区域下方的层中。 n型半导体区域的杂质浓度高于沟道形成区域并低于身体接触区域。

公开(公告)号：US07880225B2

公开(公告)日：2011-02-01

申请号：US11927375

申请日：2007-10-29

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L27/06

CPC分类号： H01L21/823487 ,  H01L27/0629

摘要： A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

摘要翻译： 形成沟槽以从源极区域的上表面到达p型外延层。 形成栅电极以埋入沟槽。 每个主体接触沟槽远离栅电极形成。 身体接触区域形成在身体接触沟槽的底部。 作为本发明的特征的n型半导体区域形成在每个体接触区域下方的层中。 n型半导体区域的杂质浓度高于沟道形成区域并低于身体接触区域。

公开(公告)号：US20090256197A1

公开(公告)日：2009-10-15

申请号：US12400436

申请日：2009-03-09

申请人： Yoshito NAKAZAWA ,  Hitoshi Matsuura

发明人： Yoshito NAKAZAWA ,  Hitoshi Matsuura

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806

摘要： Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

摘要翻译： 提供了一种在一个半导体衬底上具有功率MISFET和肖特基势垒二极管的半导体器件中的技术，其能够抑制功率MISFET的导通电阻的急剧增加，同时使肖特基势垒二极管的雪崩击穿电压更大 比功率MISFET。 在本发明中，在半导体衬底上形成两个外延层，一个具有高掺杂浓度且另一个具有低掺杂浓度的外延层，并且这两个外延层之间的边界位于相同深度或更浅的区域 沟槽的底部。

公开(公告)号：US08232161B2

公开(公告)日：2012-07-31

申请号：US12970911

申请日：2010-12-16

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L21/823

CPC分类号： H01L21/823487 ,  H01L27/0629

摘要： A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

摘要翻译： 形成沟槽以便从源极区域的上表面到达p型外延层。 形成栅电极以埋入沟槽。 每个主体接触沟槽远离栅电极形成。 身体接触区域形成在身体接触沟槽的底部。 作为本发明的特征的n型半导体区域形成在每个体接触区域下方的层中。 n型半导体区域的杂质浓度高于沟道形成区域并低于身体接触区域。

公开(公告)号：US08187941B2

公开(公告)日：2012-05-29

申请号：US13244455

申请日：2011-09-24

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

摘要翻译： 提供高性能的沟槽栅型功率晶体管。 作为栅电极的沟槽栅极形成为包括漏极层和外延层的超结结构。 在这种情况下，栅电极形成为使得外延层的上表面高于在漏极层上形成的沟道层的上表面。 然后，在沟道层和外延层的每一个上形成绝缘膜，然后去除绝缘膜的一部分，以在外延层的侧壁上形成侧壁间隔物。 随后，以侧壁间隔物作为掩模，去除沟道层的一部分和漏极层的一部分，以形成用于沟槽栅的沟槽。

公开(公告)号：US07659575B2

公开(公告)日：2010-02-09

申请号：US12138828

申请日：2008-06-13

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The technology of preventing lowering of the element breakdown voltage of a trench gate control type semiconductor element is offered. n− type epitaxial layer (drift region) formed in the main surface side of the substrate, p type semiconductor layer (channel region) formed in n− type epitaxial layer, and p− type well (electric field relaxation layer) which was formed in n− type epitaxial layer in contact with the p type semiconductor layer and whose depth is deeper than the p type semiconductor layer are included. The trench whose depth is deeper than p− type well is patterned in the substrate, and the second gate electrode is formed in the inside of the trench via the insulation film. Among the trenches in the cell area in which power MISFET is formed, one end of p− type well is formed between a plurality of cell trenches in which a second gate electrode is formed, and the other end of p− type well is formed in the peripheral region contiguous to the cell area.

摘要翻译： 提供了防止沟槽栅极控制型半导体元件的元件击穿电压降低的技术。 在衬底的主表面侧形成的n型外延层（漂移区），形成在n型外延层中的p型半导体层（沟道区），形成在p型半导体层中的p型阱（电场弛豫层） 包括与p型半导体层接触并且其深度比p型半导体层深的n型外延层。 深度比p型阱深的沟槽在衬底中被图案化，并且第二栅电极经由绝缘膜形成在沟槽的内部。 在其中形成功率MISFET的单元区域的沟槽中，在形成有第二栅电极的多个单元沟槽之间形成p型阱的一端，并且形成p型阱的另一端 与细胞区域相邻的周边区域。