公开(公告)号：US11436400B2

公开(公告)日：2022-09-06

申请号：US16895545

申请日：2020-06-08

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Qingxiang Chen ,  Long Zheng ,  Hai Jin ,  Pengcheng Yao

IPC: G06F30/331 ,  G06F16/901 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0806

Abstract: The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.

公开(公告)号：US11288221B2

公开(公告)日：2022-03-29

申请号：US16896464

申请日：2020-06-09

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Fan Zhang ,  Long Zheng ,  Hai Jin ,  Zhiyuan Shao

IPC: G06F13/40 ,  G06F9/48 ,  G06F9/50

Abstract: A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

公开(公告)号：US11263168B2

公开(公告)日：2022-03-01

申请号：US16722082

申请日：2019-12-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Hai Jin ,  Long Zheng ,  Chengbo Yang

IPC: G06F9/38 ,  G06F15/82 ,  G06F15/78 ,  G06F15/76 ,  G06F16/901

Abstract: An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

公开(公告)号：US11176046B2

公开(公告)日：2021-11-16

申请号：US16933357

申请日：2020-07-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Yu Huang ,  Long Zheng ,  Hai Jin

IPC: G06F12/00 ,  G06F12/0862 ,  H01L25/065

Abstract: The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

公开(公告)号：US10996856B2

公开(公告)日：2021-05-04

申请号：US16750655

申请日：2020-01-23

Applicant: Huazhong University of Science and Technology

Inventor： Haikun Liu ,  Xiaofei Liao ,  Hai Jin ,  Yuanyuan Ye

IPC: G03F3/06 ,  G06F3/06 ,  G11C7/10 ,  H01L25/065

Abstract: The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.