公开(公告)号：US12189950B2

公开(公告)日：2025-01-07

申请号：US18145552

申请日：2022-12-22

Applicant: Huazhong University Of Science And Technology ,  Zhejiang Lab

Inventor： Long Zheng ,  Qinggang Wang ,  Xiaofei Liao ,  Zhaozeng An ,  Hai Jin

IPC: G06F3/06

Abstract: The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

公开(公告)号：US11436400B2

公开(公告)日：2022-09-06

申请号：US16895545

申请日：2020-06-08

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Qingxiang Chen ,  Long Zheng ,  Hai Jin ,  Pengcheng Yao

IPC: G06F30/331 ,  G06F16/901 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0806

Abstract: The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.

公开(公告)号：US11288221B2

公开(公告)日：2022-03-29

申请号：US16896464

申请日：2020-06-09

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Fan Zhang ,  Long Zheng ,  Hai Jin ,  Zhiyuan Shao

IPC: G06F13/40 ,  G06F9/48 ,  G06F9/50

Abstract: A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

公开(公告)号：US11263168B2

公开(公告)日：2022-03-01

申请号：US16722082

申请日：2019-12-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Hai Jin ,  Long Zheng ,  Chengbo Yang

IPC: G06F9/38 ,  G06F15/82 ,  G06F15/78 ,  G06F15/76 ,  G06F16/901

Abstract: An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

公开(公告)号：US11176046B2

公开(公告)日：2021-11-16

申请号：US16933357

申请日：2020-07-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Yu Huang ,  Long Zheng ,  Hai Jin

IPC: G06F12/00 ,  G06F12/0862 ,  H01L25/065

Abstract: The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

公开(公告)号：US11568268B2

公开(公告)日：2023-01-31

申请号：US16748284

申请日：2020-01-21

Applicant: Huazhong University of Science and Technology

Inventor： Hai Jin ,  Xiaofei Liao ,  Long Zheng ,  Haikun Liu ,  Xi Ge

IPC: G06N3/04 ,  G06N3/10 ,  G06F9/50 ,  G06N3/08

Abstract: A deep learning heterogeneous computing method based on layer-wide memory allocation, at least comprises steps of: traversing a neural network model so as to acquire a training operational sequence and a number of layers L thereof; calculating a memory room R1 required by data involved in operation at the ith layer of the neural network model under a double-buffer configuration, where 1≤i≤L; altering a layer structure of the ith layer and updating the training operational sequence; distributing all the data across a memory room of the CPU and the memory room of the GPU according to a data placement method; performing iterative computation at each said layer successively based on the training operational sequence so as to complete neural network training.

公开(公告)号：US20210097221A1

公开(公告)日：2021-04-01

申请号：US16895545

申请日：2020-06-08

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Qingxiang Chen ,  Long Zheng ,  Hai Jin ,  Pengcheng Yao

IPC: G06F30/331 ,  G06F16/901 ,  G06F12/0806 ,  G06F9/54 ,  G06F9/38

Abstract: The present invention relates to an optimization method for graph processing based on heterogeneous FPGA data streams. The method can balance processing loads between the CPU processing module and the FPGA processing module during acceleration of graph data processing.