System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations
    11.
    发明授权
    System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations 失效
    系统使用连续的同步信号以等距周期传输数据,用于检测和发信号通路

    公开(公告)号:US06813664B2

    公开(公告)日:2004-11-02

    申请号:US10355109

    申请日:2003-01-31

    IPC分类号: G06F1336

    摘要: A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.

    摘要翻译: 一种具有执行循环数据传输的通信处理器(10)的用户终端(1)。 在发送用户数据的循环(Z,x)的循环部分(ZYK,x)期间,DP应用程序可能不访问存储器(14,15)。 在通信处理器(10)中,存储器(14,15)存储处理图像。 为了同步,通信处理器(10)在周期开始时发送周期开始中断(ZSI,x),并且在循环结束部分(ZYK,x)周期结束中断(ZEI,x) )。 一旦算术单元(5,7,8)已经访问存储器,它将释放中断。 两个连续中断之间的持续时间(DeltaT's2,1; DeltaT'2,1)用于检测访问冲突并启动适当的故障处理措施。