公开(公告)号：US06829670B1

公开(公告)日：2004-12-07

申请号：US09702755

申请日：2000-11-01

申请人： Nobutaka Nakamura

发明人： Nobutaka Nakamura

IPC分类号： G06F1336

CPC分类号： H04L1/18 ,  G06F13/4059 ,  H04L1/16

摘要： A PCI-PCI bridge is composed of two physically different controllers, i.e., a primary PCI serial transfer controller arranged at a PC, and a secondary PCI serial transfer controller arranged at a docking station. In data transfer between these controllers, preliminary transmission of block data having a block ID assigned thereto and a return of ACK having the block ID assigned thereto are performed asynchronously. The transmission party can determine which data item is the last the receiving party has received by employing a block ID assigned to NAK. When NAK is received from the receiving party, re-transmission from a block waiting for NAK is started. In this manner, data required to transmit a bus transaction between buses can be transferred accurately and speedily between two controllers.

摘要翻译： PCI-PCI桥由两个物理上不同的控制器组成，即布置在PC处的主PCI串行传输控制器，以及布置在对接站处的辅助PCI串行传输控制器。 在这些控制器之间的数据传输中，异步地执行具有分配给其的块ID的块数据的初始传输和分配给其的具有块ID的ACK的返回。 发送方可以通过使用分配给NAK的块ID来确定接收方已经接收到哪个数据项。 当从接收方接收到NAK时，从等待NAK的块开始重新发送。 以这种方式，可以在两个控制器之间准确且快速地传送在总线之间传送总线事务所需的数据。

公开(公告)号：US06820161B1

公开(公告)日：2004-11-16

申请号：US09671065

申请日：2000-09-28

申请人： Michael Anthony Perez

发明人： Michael Anthony Perez

IPC分类号： G06F1336

CPC分类号： G06F12/0802 ,  G06F12/0862 ,  G06F13/4027 ,  G06F2212/306 ,  G06F2212/6022

摘要： A method, system, and apparatus for providing data to an I/O adapter from a PCI-to-PCI bus bridge is provided. In one embodiment, once the PCI-to-PCI bus bridge receives a request for data from the I/O adapter, the PCI-to-PCI bus bridge determines whether the requested data is contained within a cached memory within the PCI-to-PCI bus bridge. If the data is contained within the cached memory, then the requested data is provided to the I/O adapter from the cached memory. If the requested data is not within the cached memory, the data is fetched from system memory, then cached in the PCI-to-PCI bus bridge, and sent to the requesting I/O adapter. To ensure that the data in the cached memory within the PCI-to-PCI bridge is not stale, signals are received, periodically or aperiodically, by the PCI-to-PCI bridge from a PCI host bridge indicating whether the data contained within the buffers is stale. If the data is stale, then in some embodiments, the contents of all the buffers are cleared, while in other embodiments, only the contents of the buffers containing data that has been indicated to be stale is cleared.

摘要翻译： 提供了一种从PCI-PCI总线桥向I / O适配器提供数据的方法，系统和装置。 在一个实施例中，一旦PCI-PCI总线桥接收到来自I / O适配器的数据请求，则PCI至PCI总线桥接器确定所请求的数据是否包含在PCI- PCI总线桥。 如果数据包含在缓存的内存中，则所请求的数据将从缓存的内存提供给I / O适配器。 如果请求的数据不在缓存的内存中，则从系统内存中取出数据，然后缓存到PCI-PCI总线桥上，并发送到请求的I / O适配器。 为了确保PCI-PCI桥接器中缓存的存储器中的数据不会过时，PCI PCI桥接器从PCI主机桥接器周期性或非周期性地接收信号，指示是否包含在缓冲器内的数据 是陈旧的 如果数据过时，则在一些实施例中，清除所有缓冲器的内容，而在其他实施例中，只有包含已被指示为陈旧的数据的缓冲器的内容被清除。

公开(公告)号：US06813664B2

公开(公告)日：2004-11-02

申请号：US10355109

申请日：2003-01-31

申请人： Christoph Koellner ,  Otmar Katzenberger ,  Joerg Mensinger ,  Heinrich Rudi

发明人： Christoph Koellner ,  Otmar Katzenberger ,  Joerg Mensinger ,  Heinrich Rudi

IPC分类号： G06F1336

CPC分类号： G05B19/0425 ,  G05B19/4185 ,  G05B2219/25021 ,  G05B2219/25158 ,  G05B2219/25274 ,  G05B2219/33248 ,  H04L12/403 ,  H04L2012/40221 ,  H04L2012/4026 ,  Y02P90/18

摘要： A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.

摘要翻译： 一种具有执行循环数据传输的通信处理器（10）的用户终端（1）。 在发送用户数据的循环（Z，x）的循环部分（ZYK，x）期间，DP应用程序可能不访问存储器（14,15）。 在通信处理器（10）中，存储器（14,15）存储处理图像。 为了同步，通信处理器（10）在周期开始时发送周期开始中断（ZSI，x），并且在循环结束部分（ZYK，x）周期结束中断（ZEI，x） ）。 一旦算术单元（5,7,8）已经访问存储器，它将释放中断。 两个连续中断之间的持续时间（DeltaT's2,1; DeltaT'2,1）用于检测访问冲突并启动适当的故障处理措施。

公开(公告)号：US06763437B1

公开(公告)日：2004-07-13

申请号：US09656529

申请日：2000-09-07

申请人： Trung Nguyen ,  Hang Nguyen ,  John W. Brooks ,  Parminder K. Gill

发明人： Trung Nguyen ,  Hang Nguyen ,  John W. Brooks ,  Parminder K. Gill

IPC分类号： G06F1336

CPC分类号： G06F13/1605 ,  G06F3/0613 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0674

摘要： A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access. In one embodiment, the second controller transmits an access request to the first controller for control of the bus to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Each of the controllers relinquishes control of the bus by placing the bus in tristate, wherein the relinquishing controller stops driving the bus.

摘要翻译： 一种通过总线提供对互连到第一控制器和第二控制器的共享存储器的访问的方法和系统，该总线具有与之相关的控制信号，用于数据传输控制和第一和第二控制器之间的通信。 第二控制器向第一控制器发送访问请求以控制总线以访问存储器。 第一控制器选择性地授权访问请求并向第二控制器发送确认; 并且在接收到确认时，第二控制器访问用于数据传送的存储器。 第一控制器具有访问存储器的第一优先级，并且第二控制器具有访问存储器的第二优先级，第二优先级低于第一优先级，使得在请求时，第一控制器选择性地将总线的控制权授予第二优先级 控制器用于存储器访问，否则第一控制器维护总线的控制以进行存储器访问。 在一个实施例中，第二控制器向第一控制器发送访问请求以控制总线访问存储器; 并且作为响应，第一控制器选择性地授予访问请求并向第二控制器发送确认。 每个控制器通过将总线放置在三态中来放弃对总线的控制，其中放弃控制器停止驱动总线。

公开(公告)号：US06738856B1

公开(公告)日：2004-05-18

申请号：US09618680

申请日：2000-07-19

申请人： Nicholas A. Milley ,  Thomas Lianza ,  Carl David Lutz

发明人： Nicholas A. Milley ,  Thomas Lianza ,  Carl David Lutz

IPC分类号： G06F1336

CPC分类号： G06F3/038 ,  G01J3/02 ,  G01J3/0264 ,  G01J3/0272 ,  G01J3/0291 ,  G01J3/463 ,  G01J3/51 ,  G06F3/033 ,  G06F3/03543 ,  Y10T307/406

摘要： A cable, adapter, or converter device is disclosed that enables a peripheral device (e.g., external display) normally connected only through a non-USB port to communicate with a host computer via a USB port in addition to its non-USB port. DDC-formatted signals from the peripheral device are converted to the appropriate format for input through the USB port, and signals transmitted to the peripheral device from the USB port are converted to the format recognizable by the external peripheral, allowing access to peripheral features via the host system.

摘要翻译： 公开了一种电缆，适配器或转换器装置，其使得能够通过非USB端口正常连接的外围设备（例如，外部显示器）除了其非USB端口之外还经由USB端口与主计算机进行通信。 来自外围设备的DDC格式的信号被转换成用于通过USB端口输入的适当格式，并且从USB端口传输到外围设备的信号被转换为外部外围设备可识别的格式，允许通过外部设备访问外围设备 主机系统。

公开(公告)号：US06718425B1

公开(公告)日：2004-04-06

申请号：US09583892

申请日：2000-05-31

申请人： Andrew J. Pajakowski ,  Jon E. Krutulis ,  Alex Knight ,  Michael W. Phillips ,  Michael Kimball ,  Lee Gene Shipman ,  Joe Beitzinger

发明人： Andrew J. Pajakowski ,  Jon E. Krutulis ,  Alex Knight ,  Michael W. Phillips ,  Michael Kimball ,  Lee Gene Shipman ,  Joe Beitzinger

IPC分类号： G06F1336

CPC分类号： G01M17/00 ,  G05B23/0283 ,  G07C5/008

摘要： A novel and improved engine data system for collecting, displaying and analyzing engine/vehicle data is provided. The system have advantageously results in a more effective, convenient, portable and low cost method of monitoring and processing vehicle data. The vehicle data system includes a handheld computer containing operating system software adapted to operate the handheld computer in accordance with a data protocol different from a vehicle bus protocol and a handheld microprocessor for executing the operating system software. The system importantly includes an adapter for creating a data pathway between a vehicle bus connector and an external data port provided on the handheld computer which is physically incompatible with the engine bus connector. The adapter includes a data port connector for connection with the external data port, a bus compatible connector for connection with the engine bus connector, a battery power supply separate from the power supply of the handheld compuer and an adapter microprocessor powered by the battery power supply and connected via the data pathway with the bus compatible connector for protocol conversion of the data received from the engine bus. An engine data adapter system for creating a data pathway between the engine data bus and the handheld computer while determining the start and stop of messages received from the data bus and adding message identifiers to the engine data so as to minimize the required data processing by the handheld computer.

摘要翻译： 提供了一种用于收集，显示和分析发动机/车辆数据的新颖和改进的发动机数据系统。 该系统有利地导致监视和处理车辆数据的更有效，便利，便携和低成本的方法。 车辆数据系统包括手持计算机，其包含适于根据与车辆总线协议不同的数据协议和用于执行操作系统软件的手持式微处理器操作手持式计算机的操作系统软件。 该系统重要地包括用于在车辆总线连接器和设置在与发动机总线连接器物理不兼容的手持式计算机上的外部数据端口之间创建数据通路的适配器。 适配器包括用于与外部数据端口连接的数据端口连接器，用于与发动机总线连接器连接的总线兼容连接器，与手持式压缩机的电源分开的电池电源以及由电池电源供电的适配器微处理器 并通过数据通道与总线兼容连接器连接，用于从发动机总线接收的数据进行协议转换。 一种引擎数据适配器系统，用于在确定从数据总线接收到的消息的开始和停止以及向引擎数据添加消息标识符之间创建引擎数据总线和手持式计算机之间的数据通路，以便最小化所需的数据处理 手提电脑。

公开(公告)号：US06701399B1

公开(公告)日：2004-03-02

申请号：US09514980

申请日：2000-02-29

申请人： Howard M. Brown

发明人： Howard M. Brown

IPC分类号： G06F1336

CPC分类号： G06F13/3625

摘要： A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority. In another embodiment, queued isochronous transactions are only processed at the start of a new frame if they are from two frames prior to the new frame.

摘要翻译： 调度共享总线上的多个异步和等时事务，使异步延迟最小化，同时为同步事务提供最大等待时间。 这是通过将分配的共享总线时间分成等长的帧来实现的。 当接收到总线请求时，该技术确定当前帧中的总线请求是用于异步事务还是等时事务。 如果存在异步事务总线请求，则处理它，否则处理同步事务总线请求。 如果在异步事务处理当前正在接收到等时事务的总线请求将排队。 在当前帧时间结束之前，异步事务被赋予优先权。 在一个实施例中，在新帧（其变为当前帧）的开始，在给予优先权的当前帧的异步事务之前处理任何排队的同步事务。 在另一个实施例中，排队的等时事务仅在新帧开始时被处理，如果它们来自新帧之前的两个帧。

公开(公告)号：US06671765B1

公开(公告)日：2003-12-30

申请号：US09506613

申请日：2000-02-18

申请人： Magnus G. Karlsson ,  Gregory Lee Christison

发明人： Magnus G. Karlsson ,  Gregory Lee Christison

IPC分类号： G06F1336

CPC分类号： G06F9/445

摘要： A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit (136) coupled between the USB host (12) and the circuitry (32) for providing a capability to the USB host. The USB interface circuit comprises a memory area (106) comprising a code overlay endpoint (1061) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry (150-163) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space. The circuitry for communicating is operable to communicate a code block from the code overlay endpoint to the address space after a start-up time of the USB function device.

摘要翻译： 一种用于耦合到USB主机（12）的USB功能设备（14）。 USB功能设备（14）包括用于向USB主机提供能力的电路（32），其中用于该能力的电路包括地址空间。 USB功能设备还包括耦合在USB主机（12）和电路（32）之间的USB接口电路（136），用于向USB主机提供能力。 USB接口电路包括存储区域（106），该存储器区域（106）包括USB主机可访问的代码覆盖端点（1061），用于将两个或更多个代码块写入代码覆盖端点。 USB接口电路还包括用于将代码块中的第一代码块从代码覆盖端点传送到地址空间的电路（150-163），并且用于随后将代码块中的第二代码块从代码覆盖端点传送到地址空间。 用于通信的电路可操作以在USB功能设备的启动时间之后将码块从代码覆盖端点传送到地址空间。

公开(公告)号：US06643726B1

公开(公告)日：2003-11-04

申请号：US09376820

申请日：1999-08-18

申请人： Niteen Patkar ,  Ali Alasti ,  Don Van Dyke ,  Korbin Van Dyke ,  Shalesh Thusoo ,  Stephen C. Purcell ,  Govind Malalur

发明人： Niteen Patkar ,  Ali Alasti ,  Don Van Dyke ,  Korbin Van Dyke ,  Shalesh Thusoo ,  Stephen C. Purcell ,  Govind Malalur

IPC分类号： G06F1336

CPC分类号： G06F13/368

摘要： An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

摘要翻译： 集成计算系统包括形成在衬底上的至少一个处理器，其中处理器以处理器速率工作。 集成计算系统还包括耦合到至少一个处理器并形成在基板上的全局总线。 全局总线以等于或大于处理速率的速率支持事务（例如，数据，操作指令和/或控制信令传送）。 集成计算系统还包括可操作地耦合到全局总线并形成在基板上的设备网关和存储器网关。 设备网关为全局总线的至少一个设备（例如，内部或外部）提供接口。 存储器网关提供全局总线和存储器之间的接口。

公开(公告)号：US06587911B1

公开(公告)日：2003-07-01

申请号：US09551226

申请日：2000-04-17

申请人： Harumi Kawamura ,  Yasuhiro Takada

发明人： Harumi Kawamura ,  Yasuhiro Takada

IPC分类号： G06F1336

CPC分类号： H04L12/56

摘要： Apparatus for use when a format which can be transmitted by a transmission device is not equal to a format which can be received by a reception device that makes it possible to correctly perform data transmission includes a controller for controlling transmission that determines a transmission format with reference to a transmittable format of a source device and a receivable format of a destination device and instructs the source device to perform data transmission in the determined transmission format. When the data format which can be transmitted by the source device cannot be received by the destination device, the controller determines a transmission data format with reference to a data format which can be converted by a format converter connected to a bus and having a data format converting function and instructs the source device to transmit data to the format converter. The format converter which receives the data transmits the data to the destination device.

摘要翻译： 当发送装置可以发送的格式不等于接收装置能够正确地进行数据发送的格式时，使用的装置包括控制发送的控制器，该控制器用于参考确定发送格式 以源设备的可发送格式和目的地设备的可接收格式，并指示源设备以确定的传输格式执行数据传输。 当目的地设备不能接收到源设备可以发送的数据格式时，控制器将参照可由连接到总线的格式转换器转换并具有数据格式的数据格式来确定发送数据格式 转换功能并指示源设备向格式转换器发送数据。 接收数据的格式转换器将数据发送到目的地设备。