公开(公告)号：US10650140B2

公开(公告)日：2020-05-12

申请号：US14671194

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Abhay S. Kanhere ,  Paul Caprioli

IPC: G06F21/54 ,  G06F9/50 ,  G06F21/12 ,  G06F21/56 ,  G06F9/48 ,  G06F21/53 ,  G06F21/51 ,  G06F21/52 ,  G06F9/455

Abstract: A data processing system (DPS) supports control-flow integrity (CFI). The DPS comprises a processing element with a CFI enforcement mechanism that supports one or more CFI instructions. The DPS also comprises at least one machine-accessible medium responsive to the processing element. Managed code in the machine-accessible medium is configured (a) to execute in a managed runtime environment (MRE) in the data processing system, and (b) to transfer control out from the MRE to unmanaged code, in response to a transfer control statement in the managed code. The machine-accessible medium also comprises a binary translator which, when executed, converts unmanaged code in the data processing system into hardened unmanaged code (HUC) by including CFI features in the HUC. The CFI features comprise one or more CFI instructions to utilize the CFI enforcement mechanism of the processing element for transfers of control initiated by the HUC. Other embodiments are described and claimed.

公开(公告)号：US09588766B2

公开(公告)日：2017-03-07

申请号：US13630154

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Paul Caprioli ,  Abhay S. Kanhere ,  Jeffrey J. Cook ,  Muawya M. Al-Otoom

IPC: G06F12/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/3887 ,  G06F9/3893

Abstract: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

Abstract translation: 由处理器执行向量减少指令以对数据元素阵列提供有效的减少操作。 处理器包括向量寄存器。 每个向量寄存器被分成多个通道，每个通道存储相同数量的数据元素。 处理器还包括执行电路，其接收向量减少指令，以使用缩减运算符将存储在源操作数中的数据元素的阵列减少到目标操作数的结果。 源操作数和目标操作数中的每一个都是向量寄存器之一。 响应于向量减少指令，执行电路将减法运算符应用于每个通道中的两个数据元素，并且当存在每个通道中的至少一个数据元素时，移位一个或多个剩余数据元素。

公开(公告)号：US20150339109A1

公开(公告)日：2015-11-26

申请号：US14709154

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Abhay S. Kanhere ,  Saurabh Shukla ,  Suriya Subramanian ,  Paul Caprioli

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F9/45516 ,  G06F11/1405 ,  G06F2201/805

Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code.

Abstract translation: 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：将第一指令插入到优化的代码中，以使得在执行优化的代码的区域之前将第一状态的寄存器的第一部分保存到存储器; 并且保持指示与从优化代码的状态恢复相关联地恢复处于第一状态的寄存器的第二部分的方式的值。