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    Control-flow integrity with managed code and unmanaged code
    1.
    发明授权
    Control-flow integrity with managed code and unmanaged code 有权

    公开(公告)号：US10650140B2

    公开(公告)日：2020-05-12

    申请号：US14671194

    申请日：2015-03-27

    Applicant: INTEL CORPORATION

    Inventor： Abhay S. Kanhere ,  Paul Caprioli

    IPC: G06F21/54 ,  G06F9/50 ,  G06F21/12 ,  G06F21/56 ,  G06F9/48 ,  G06F21/53 ,  G06F21/51 ,  G06F21/52 ,  G06F9/455

    Abstract: A data processing system (DPS) supports control-flow integrity (CFI). The DPS comprises a processing element with a CFI enforcement mechanism that supports one or more CFI instructions. The DPS also comprises at least one machine-accessible medium responsive to the processing element. Managed code in the machine-accessible medium is configured (a) to execute in a managed runtime environment (MRE) in the data processing system, and (b) to transfer control out from the MRE to unmanaged code, in response to a transfer control statement in the managed code. The machine-accessible medium also comprises a binary translator which, when executed, converts unmanaged code in the data processing system into hardened unmanaged code (HUC) by including CFI features in the HUC. The CFI features comprise one or more CFI instructions to utilize the CFI enforcement mechanism of the processing element for transfers of control initiated by the HUC. Other embodiments are described and claimed.

    TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION SYSTEMS
    2.
    发明申请
    TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION SYSTEMS 审中-公开

    公开(公告)号：US20190235849A1

    公开(公告)日：2019-08-01

    申请号：US16378641

    申请日：2019-04-09

    Applicant: Intel Corporation

    Inventor： Paul Caprioli ,  Jeffrey J. Cook

    IPC: G06F8/52 ,  G06F12/02 ,  G06F9/455

    CPC classification number: G06F8/52 ,  G06F9/30 ,  G06F9/45525 ,  G06F11/3409 ,  G06F12/023

    Abstract: Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a translation cache. The cost-benefit metric is indicative of translation cost and performance benefit associated with the translated code block. The translation cost may be determined by measuring translation time of the translated code block. The cost-benefit metric may be calculated using a weighted cost-benefit function based on an expected workload of the computing device. In response to determining to free space in the translation cache, the computing device determines whether to discard each translated code block as a function of the cost-benefit metric. In response to determining to free space in the translation cache, the computing device may increment an iteration count and skip each translated code block if the iteration count modulo the corresponding cost-benefit metric is non-zero. Other embodiments are described and claimed.

    Accelerated interlane vector reduction instructions
    3.
    发明授权
    Accelerated interlane vector reduction instructions 有权
    加速交错向量减少指令

    公开(公告)号：US09588766B2

    公开(公告)日：2017-03-07

    申请号：US13630154

    申请日：2012-09-28

    Applicant: Intel Corporation

    Inventor： Paul Caprioli ,  Abhay S. Kanhere ,  Jeffrey J. Cook ,  Muawya M. Al-Otoom

    IPC: G06F12/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/3887 ,  G06F9/3893

    Abstract: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

    Abstract translation: 由处理器执行向量减少指令以对数据元素阵列提供有效的减少操作。 处理器包括向量寄存器。 每个向量寄存器被分成多个通道，每个通道存储相同数量的数据元素。 处理器还包括执行电路，其接收向量减少指令，以使用缩减运算符将存储在源操作数中的数据元素的阵列减少到目标操作数的结果。 源操作数和目标操作数中的每一个都是向量寄存器之一。 响应于向量减少指令，执行电路将减法运算符应用于每个通道中的两个数据元素，并且当存在每个通道中的至少一个数据元素时，移位一个或多个剩余数据元素。

    STATE RECOVERY METHODS AND APPARATUS FOR COMPUTING PLATFORMS
    5.
    发明申请
    STATE RECOVERY METHODS AND APPARATUS FOR COMPUTING PLATFORMS 有权
    用于计算平台的状态恢复方法和装置

    公开(公告)号：US20150339109A1

    公开(公告)日：2015-11-26

    申请号：US14709154

    申请日：2015-05-11

    Applicant: Intel Corporation

    Inventor： Abhay S. Kanhere ,  Saurabh Shukla ,  Suriya Subramanian ,  Paul Caprioli

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F9/45516 ,  G06F11/1405 ,  G06F2201/805

    Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code.

    Abstract translation: 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：将第一指令插入到优化的代码中，以使得在执行优化的代码的区域之前将第一状态的寄存器的第一部分保存到存储器; 并且保持指示与从优化代码的状态恢复相关联地恢复处于第一状态的寄存器的第二部分的方式的值。

    STATE RECOVERY METHODS AND APPARATUS FOR COMPUTING PLATFORMS
    8.
    发明申请
    STATE RECOVERY METHODS AND APPARATUS FOR COMPUTING PLATFORMS 审中-公开
    用于计算平台的状态恢复方法和装置

    公开(公告)号：US20170046140A1

    公开(公告)日：2017-02-16

    申请号：US15335709

    申请日：2016-10-27

    Applicant: Intel Corporation

    Inventor： Abhay S. Kanhere ,  Saurabh Shukla ,  Suriya Subramanian ,  Paul Caprioli

    IPC: G06F9/45 ,  G06F9/455 ,  G06F11/14

    CPC classification number: G06F8/443 ,  G06F9/45516 ,  G06F11/1405 ,  G06F2201/805

    Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting, with a processor, a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code, maintaining, with the processor, a first indication of a first manner in which the first portion of the register is to be restored in connection with a state recovery after execution of the region of the optimized code, and maintaining, with the processor, a second indication of a second manner in which a second portion of the register is to be restored in connection with the state recovery after execution of the region of the optimized code.

    Abstract translation: 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：利用处理器将第一指令插入到优化的代码中，以使得在执行优化代码的区域之前将处于第一状态的寄存器的第一部分保存到存储器， 与执行优化代码的区域之后的状态恢复相关联地恢复寄存器的第一部分的第一方式的第一指示，并且用处理器维持第二方式的第二指示，其中第二指示 寄存器的第二部分将在执行优化代码的区域之后与状态恢复相关联地恢复。

    System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers
    9.
    发明授权
    System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers 有权
    具有代码转换的加载指令的系统和方法具有访问权限，以指示来自寄存器的加载内容的失败

    公开(公告)号：US09280492B2

    公开(公告)日：2016-03-08

    申请号：US14142834

    申请日：2013-12-28

    Applicant: Intel Corporation

    Inventor： Paul Caprioli ,  Alexandre Farcy

    IPC: G06F3/00 ,  G06F12/14 ,  G06F9/30

    CPC classification number: G06F12/1458 ,  G06F9/30043

    Abstract: Embodiments of an invention for a load instruction for code conversion are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having a source operand to indicate a source location and a destination operand to indicate a destination location. The execution unit is to execute the instruction. Execution of the instruction includes checking the access permissions of the source location and loading content from the source location into the destination location if the access permissions of the source location indicate that the content is executable.

    Abstract translation: 公开了用于代码转换的加载指令的发明的实施例。 在一个实施例中，处理器包括指令单元和执行单元。 指令单元接收具有源操作数的指令以指示源位置和目的地操作数以指示目的地位置。 执行单元执行指令。 如果源位置的访问权限指示内容是可执行的，则执行指令包括检查源位置的访问权限并将内容从源位置加载到目的地位置。

    RETURN-TARGET RESTRICTIVE RETURN FROM PROCEDURE INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    10.
    发明申请
    RETURN-TARGET RESTRICTIVE RETURN FROM PROCEDURE INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 有权
    程序指令，处理程序，方法和系统的返回目标限制性返回

    公开(公告)号：US20150278516A1

    公开(公告)日：2015-10-01

    申请号：US14229822

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Paul Caprioli

    IPC: G06F21/54 ,  G06F9/30

    CPC classification number: G06F21/54 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30145 ,  G06F2221/034

    Abstract: A processor includes a decode unit to decode a return target restrictive return from procedure (RTR return) instruction. A return target restriction unit is responsive to the RTR return instruction to determine whether to restrict an attempt by the RTR return instruction to make a control flow transfer to an instruction at a return address corresponding to the RTR return instruction. The determination is based on compatibility of a type of the instruction at the return address with the RTR return instruction and based on compatibility of first return target restrictive information (RTR information) of the RTR return instruction with second RTR information of the instruction at the return address. A control flow transfer unit is responsive to the RTR return instruction to transfer control flow to the instruction at the return address when the return target restriction unit determines not to restrict the attempt.

    Abstract translation: 处理器包括解码单元，用于解码从过程（RTR返回）指令返回目标限制性返回。 返回目标限制单元响应于RTR返回指令来确定是否限制RTR返回指令的尝试以使控制流传送到与RTR返回指令相对应的返回地址处的指令。 该确定是基于返回地址处的指令类型与RTR返回指令的兼容性，并且基于RTR返回指令的第一返回目标限制信息（RTR信息）与返回指令的第二RTR信息的兼容性 地址。 当返回目标限制单元确定不限制该尝试时，控制流传送单元响应于RTR返回指令将控制流传送到返回地址处的指令。

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