公开(公告)号：US10728178B2

公开(公告)日：2020-07-28

申请号：US15776661

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Albert S. Cheng

IPC: H04L12/931 ,  H04L12/801

Abstract: Apparatuses and methods associated with distributing congestion information in a switch are provided. In embodiments, the switch includes a plurality of ports arranged in a plurality of rows and a plurality of columns. The switch further includes a plurality of daisy-chain buses, individual daisy-chain buses coupling the ports of a respective row to one another in a daisy-chain. The switch further includes a plurality of column buses, individual column buses coupling an individual port of the plurality of ports to the other ports of the respective column. Individual ports of a respective row receive congestion information from the other ports of the row via the respective daisy-chain bus and pass the congestion information to the other ports of the respective column via the respective column bus. Other embodiments may be described and/or claimed.

公开(公告)号：US20190007319A1

公开(公告)日：2019-01-03

申请号：US15639816

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Scott S. Diesing ,  Michael A. Parker ,  Albert S. Cheng ,  Nan Ni

IPC: H04L12/803

Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.