公开(公告)号：US10911366B2

公开(公告)日：2021-02-02

申请号：US15639816

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Scott S. Diesing ,  Michael A. Parker ,  Albert S. Cheng ,  Nan Ni

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/773 ,  H04L12/803 ,  H04L12/863 ,  H04L12/867 ,  H04L12/869 ,  H04L12/933 ,  H04L12/935

Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.

公开(公告)号：US20190007319A1

公开(公告)日：2019-01-03

申请号：US15639816

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Scott S. Diesing ,  Michael A. Parker ,  Albert S. Cheng ,  Nan Ni

IPC: H04L12/803

Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.

公开(公告)号：US10333848B2

公开(公告)日：2019-06-25

申请号：US15200453

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  Eric R. Borch ,  Michael A. Parker ,  Scott S. Diesing

IPC: H04L12/801 ,  H04L12/26 ,  H04L12/835 ,  H04L12/935

Abstract: Technologies for adaptive routing using throughput estimation that includes a network switch. The network switch is configured to determine an adjusted average saturation count for each output buffer queue as a function of a present value of a saturation counter of a corresponding output buffer queue and a weighted average saturation count and a running average saturation count for each of the plurality of output buffer queues as a function of the corresponding captured present value and the adjusted average saturation count. The network switch is further configured to determine a congestion rate value for each output buffer queue and a total congestion value as a function of the congestion rate values and a standard occupancy congestion corresponding to a respective one of the plurality of output buffer queues. Other embodiments are described herein.