公开(公告)号：US09397792B2

公开(公告)日：2016-07-19

申请号：US14099323

申请日：2013-12-06

Applicant: Intel Corporation

Inventor： Mark S. Birrittella

IPC: H04L1/18 ,  H04L1/16

CPC classification number: H04L1/1657 ,  G06F9/00 ,  H04L1/08 ,  H04L1/1867 ,  H04L1/1874 ,  H04L67/104

Abstract: Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to facilitate confirmed error-free delivery of link-layer packets through use of implicit ACKs, while also providing retransmission of packets for which errors are detected and guaranteeing the link control data is either successfully received or data transfer over the link is prevented. In conjunction with transmitting packets, reliable packets are copied into sequential slots in a replay buffer. Each link interface tracks the slot at which each reliable packet is buffered, and in response to detection of an error, a retry request is sent to the transmit-side to retransmit the errant packet. The previously buffered copy of the errant packet is retrieved from the replay buffer and retransmitted. Through use of a link roundtrip detection mechanism, absence of a retry request by the time a replay buffer has returned to the slot of a reliable packet (plus a predetermined number of additional transfer cycles, if applicable) provides an implicit ACK that the packet was received without error.

Abstract translation: 用于实现使用隐式确认（ACK）的链路层重试协议的方法，装置和系统。 对等链路接口被配置为通过使用隐式ACK来促进确认的无差错地传送链路层分组，同时还提供重传检测到错误的分组，并且确保链路控制数据被成功接收或通过链路的数据传送 被阻止 结合发送分组，可靠的分组被复制到重播缓冲器中的顺序时隙中。 每个链路接口跟踪缓冲每个可靠分组的时隙，并且响应于检测到错误，重发请求被发送到发送侧以重传错误分组。 从重放缓冲区中检索先前缓存的错误数据包的副本并重发。 通过使用链路往返检测机制，在重播缓冲器已经返回到可靠分组的时隙（加上预定数量的附加传输周期（如果适用）的时候）没有重试请求提供了分组是 收到没有错误。

公开(公告)号：US20160132072A1

公开(公告)日：2016-05-12

申请号：US14537618

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： Mark S. Birrittella

IPC: G06F1/12

CPC classification number: G06F1/12 ,  H04J3/0685 ,  H04J3/0697 ,  H04L7/0012 ,  H04L7/005

Abstract: Embodiments of the present disclosure are directed toward signal synchronization in a link layer interconnect fabric. In one instance, an apparatus with logic for signal synchronization may include a clock synchronization logic to compare a core clock of the apparatus having a core clock frequency against a transmission clock of the apparatus having a first frequency or a reception clock of the apparatus having a second frequency, and, based on results of the comparison, generate a synchronized link transfer transmission clock or a synchronized link transfer reception clock respectively. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及链路层互连结构中的信号同步。 在一种情况下，具有用于信号同步的逻辑的装置可以包括时钟同步逻辑，用于将具有核心时钟频率的装置的核心时钟与具有第一频率的装置的传输时钟或装置的接收时钟进行比较 第二频率，并且基于比较结果分别产生同步的链路传输传输时钟或同步的链路传送接收时钟。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09325449B2

公开(公告)日：2016-04-26

申请号：US14099345

申请日：2013-12-06

Applicant: Intel Corporation

Inventor： Mark S. Birrittella

IPC: H03M13/00 ,  G06F11/10 ,  H04L1/00 ,  H03M13/09

CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0058 ,  H04L1/0061 ,  H04L1/0071 ,  H04L1/08 ,  H04L1/1607 ,  H04L1/1657 ,  H04L1/1874

Abstract: Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.

Abstract translation: 用于检测车道错误和消除多车道链路中的错误车道的方法，装置和系统。 包括链路分组的数据被分割成多个比特流并且并行地在多通道链路的各个通道上传输。 比特流数据在接收器端口的多个接收通道处被接收并被处理以重新组合链路分组并且计算在每个通道上接收的数据上的CRC。 链路分组包括与接收到的CRC进行比较的发送CRC，以检测链路分组错误。 在检测到链路分组错误时，存储每通道或每个传输组CRC值，并且发出重试请求以重新发送坏数据包。 结合接收重传的分组，每通道或每个传输组CRC值在接收的数据上重新计算，并与存储的每通道或每个传输组CRC值进行比较，以检测引起链路分组错误的通道。