公开(公告)号：US20230353341A1

公开(公告)日：2023-11-02

申请号：US18350220

申请日：2023-07-11

申请人： SK hynix Inc.

发明人： Yong Tae JEON ,  Dae Sik PARK ,  Jae Young JANG ,  Byung Cheol KANG ,  Seung Duk CHO

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/005 ,  H04L7/033 ,  H04L7/0091 ,  H04L7/0079

摘要： Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

公开(公告)号：US20180300272A1

公开(公告)日：2018-10-18

申请号：US16018085

申请日：2018-06-26

申请人： Nephos (Hefei) Co. Ltd.

发明人： Yi-Hung Chen ,  Yuan-Chin Liu

IPC分类号： G06F13/362 ,  H04L7/00 ,  G06F13/40

CPC分类号： G06F13/362 ,  G06F13/4022 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/005

摘要： A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

公开(公告)号：US20180175830A1

公开(公告)日：2018-06-21

申请号：US15553909

申请日：2017-01-16

申请人： NTT ELECTRONICS CORPORATION ,  NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： Yasuharu ONUMA ,  Etsushi YAMAZAKI ,  Kazuhito TAKEI ,  Osamu ISHIDA ,  Kengo HORIKOSHI ,  Mitsuteru YOSHIDA ,  Yoshiaki KISAKA ,  Masahito TOMIZAWA

IPC分类号： H03H17/02 ,  H04L7/00

CPC分类号： H03H17/0227 ,  H03H17/0213 ,  H03H17/0275 ,  H03H17/0685 ,  H03H2017/0214 ,  H03H2017/0245 ,  H03H2017/0247 ,  H03H2017/0298 ,  H04L7/0029 ,  H04L7/005 ,  H04L7/0087

摘要： A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

公开(公告)号：US09825754B2

公开(公告)日：2017-11-21

申请号：US15188263

申请日：2016-06-21

申请人： Microchip Technology Incorporated

发明人： Roshan Samuel

IPC分类号： H04L7/00 ,  H04L12/24 ,  H04L12/26 ,  H04L29/06 ,  G06F13/42

CPC分类号： H04L7/0012 ,  G06F13/4295 ,  H04L7/005 ,  H04L41/0681 ,  H04L43/16 ,  H04L69/28

摘要： A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.

公开(公告)号：US20170317862A1

公开(公告)日：2017-11-02

申请号：US15651364

申请日：2017-07-17

申请人： ATI Technologies ULC

发明人： Andy Sung ,  Leon Lai ,  Daniel Wang

IPC分类号： H04L27/00 ,  H04L7/00 ,  G06F5/06

CPC分类号： H04L27/00 ,  G06F5/06 ,  H04L7/005

摘要： A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

公开(公告)号：US09712353B2

公开(公告)日：2017-07-18

申请号：US13632751

申请日：2012-10-01

申请人： ATI Technologies ULC

发明人： Andy Sung ,  Leon Lai ,  Daniel Wang

IPC分类号： H04L12/28 ,  H04L27/00 ,  G06F5/06 ,  H04L7/00

CPC分类号： H04L27/00 ,  G06F5/06 ,  H04L7/005

摘要： A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

公开(公告)号：US09660799B1

公开(公告)日：2017-05-23

申请号：US14950319

申请日：2015-11-24

申请人： Intel Corporation

发明人： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC分类号： G06F1/06 ,  H04L7/033 ,  H04L7/00

CPC分类号： H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

摘要： Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US09444615B2

公开(公告)日：2016-09-13

申请号：US14235242

申请日：2011-07-25

申请人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

发明人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

IPC分类号： H04L7/033 ,  H04L7/00 ,  H03L7/08 ,  H04L25/20

CPC分类号： H04L7/0331 ,  H03L7/0807 ,  H04L7/0025 ,  H04L7/0045 ,  H04L7/005 ,  H04L7/033 ,  H04L25/20

摘要： A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

摘要翻译： 提供了一种用于减少数字信号中的抖动的电路，包括时钟和数据恢复级，用于接收输入数据信号，并响应于此生成恢复的数据信号，恢复的时钟信号和未滤波的内插器代码; 滤波器级，用于接收未滤波的内插器代码并响应于其产生经滤波的时钟信号; 以及存储组件，用于接收恢复的数据信号，恢复的时钟信号和经滤波的时钟信号; 使用恢复的时钟信号对恢复的数据信号进行采样; 存储所得到的采样位; 并通过选择使用滤波的时钟信号所存储的位产生输出数据信号。

公开(公告)号：US20150341159A1

公开(公告)日：2015-11-26

申请号：US14817996

申请日：2015-08-04

申请人： STMicroelectronics N.V.

发明人： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC分类号： H04L7/00 ,  H04L7/02

CPC分类号： H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

摘要： An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

摘要翻译： 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

公开(公告)号：US20150312022A1

公开(公告)日：2015-10-29

申请号：US13800914

申请日：2013-03-13

申请人： SEMTECH CORPORATION

发明人： Paul Spencer Milton

IPC分类号： H04L7/00

CPC分类号： H04L7/0016 ,  G06F1/3209 ,  G06F1/3287 ,  H04J3/04 ,  H04J3/0697 ,  H04L7/005 ,  Y02D10/171

摘要： Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.

摘要翻译： 这里描述了用于降低数据通信/电信多路复用器和解复用器中的功耗，延迟和芯片复杂度的系统和方法。 在标准数字核心数据路径周围或代替标准数字核心数据路径添加高频模拟域数据路径允许消除将数据流的数据速率降低到标准数字内核所需的数据速率所需的解复用和复用阶段。 由于数据操作所需的顺序元件的工作频率较高，延迟也会降低。 数字内核在不使用时可以关闭电源，必要时可以激活。