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    DATA TRANSMISSION BEETWEEN ASYCHRONOUS ENVIRONMENTS
    4.
    发明申请
    DATA TRANSMISSION BEETWEEN ASYCHRONOUS ENVIRONMENTS 审中-公开

    公开(公告)号：US20170317862A1

    公开(公告)日：2017-11-02

    申请号：US15651364

    申请日：2017-07-17

    申请人： ATI Technologies ULC

    发明人： Andy Sung ,  Leon Lai ,  Daniel Wang

    IPC分类号： H04L27/00 ,  H04L7/00 ,  G06F5/06

    CPC分类号： H04L27/00 ,  G06F5/06 ,  H04L7/005

    摘要： A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

    Low latency digital jitter termination for repeater circuits
    7.
    发明授权
    Low latency digital jitter termination for repeater circuits 有权
    中继器电路的低延迟数字抖动终端

    公开(公告)号：US09444615B2

    公开(公告)日：2016-09-13

    申请号：US14235242

    申请日：2011-07-25

    申请人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

    发明人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

    IPC分类号： H04L7/033 ,  H04L7/00 ,  H03L7/08 ,  H04L25/20

    CPC分类号： H04L7/0331 ,  H03L7/0807 ,  H04L7/0025 ,  H04L7/0045 ,  H04L7/005 ,  H04L7/033 ,  H04L25/20

    摘要： A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

    摘要翻译： 提供了一种用于减少数字信号中的抖动的电路，包括时钟和数据恢复级，用于接收输入数据信号，并响应于此生成恢复的数据信号，恢复的时钟信号和未滤波的内插器代码; 滤波器级，用于接收未滤波的内插器代码并响应于其产生经滤波的时钟信号; 以及存储组件，用于接收恢复的数据信号，恢复的时钟信号和经滤波的时钟信号; 使用恢复的时钟信号对恢复的数据信号进行采样; 存储所得到的采样位; 并通过选择使用滤波的时钟信号所存储的位产生输出数据信号。

    NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD
    8.
    发明申请
    NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD 审中-公开
    噪声形状的插值器和减法器装置和方法

    公开(公告)号：US20150341159A1

    公开(公告)日：2015-11-26

    申请号：US14817996

    申请日：2015-08-04

    申请人： STMicroelectronics N.V.

    发明人： Steven R. Norsworthy ,  Jason Rupert Redgrave

    IPC分类号： H04L7/00 ,  H04L7/02

    CPC分类号： H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

    摘要： An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

    摘要翻译： 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

    LOW-POWER, LOW-LATENCY ARCHITECTURE FOR TELECOM AND DATACOM MULTIPLEXERS AND DEMULTIPLEXERS
    9.
    发明申请
    LOW-POWER, LOW-LATENCY ARCHITECTURE FOR TELECOM AND DATACOM MULTIPLEXERS AND DEMULTIPLEXERS 有权
    用于电信和数字多路复用器和解复用器的低功耗，低功耗架构

    公开(公告)号：US20150312022A1

    公开(公告)日：2015-10-29

    申请号：US13800914

    申请日：2013-03-13

    申请人： SEMTECH CORPORATION

    发明人： Paul Spencer Milton

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0016 ,  G06F1/3209 ,  G06F1/3287 ,  H04J3/04 ,  H04J3/0697 ,  H04L7/005 ,  Y02D10/171

    摘要： Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.

    摘要翻译： 这里描述了用于降低数据通信/电信多路复用器和解复用器中的功耗，延迟和芯片复杂度的系统和方法。 在标准数字核心数据路径周围或代替标准数字核心数据路径添加高频模拟域数据路径允许消除将数据流的数据速率降低到标准数字内核所需的数据速率所需的解复用和复用阶段。 由于数据操作所需的顺序元件的工作频率较高，延迟也会降低。 数字内核在不使用时可以关闭电源，必要时可以激活。

    OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER
    10.
    发明申请
    OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER 有权
    补偿没有弹性缓冲区的频率差异

    公开(公告)号：US20150280898A1

    公开(公告)日：2015-10-01

    申请号：US14231499

    申请日：2014-03-31

    申请人： STMicroelectronics International N.V.

    发明人： Abhishek Chowdhary ,  Vivek Uppal ,  Alok Kaushik ,  Sajal Kumar Mandal ,  Tapas Nandy ,  Sanjeev Chopra

    IPC分类号： H04L7/00 ,  H04L7/033 ,  H03L7/091

    CPC分类号： H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

    摘要： A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

    摘要翻译： 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。