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公开(公告)号：US10296416B2
公开(公告)日：2019-05-21
申请号：US15201438
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US10009339B2
公开(公告)日：2018-06-26
申请号：US15086214
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Sergiu D. Ghetie , Neeraj S. Upasani , Vijaya K. Boddu , Kenneth Young , Daniel G. Borkowski , Won Lee , Shahrokh Shahidzadeh , Samie B. Samaan
CPC classification number: H04L63/083 , G06F21/44 , G06F21/88 , G06K19/0723 , H04L63/0853 , H04L63/0876 , H04W12/00407 , H04W12/06
Abstract: In one embodiment, a processor includes: a first die including at least one processor core to execute instructions and a non-volatile storage to store an identifier to be provisioned into the processor during manufacture; a second die to couple to the first die, the second die including a wireless circuit and a second non-volatile storage; and a wireless interface to couple to the second die to enable wireless communication with a wireless device. The processor may be disabled if the identifier is not stored in the second non-volatile storage. Other embodiments are described and claimed.
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