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公开(公告)号：US20200341921A1
公开(公告)日：2020-10-29
申请号：US15931868
申请日：2020-05-14
申请人： Intel Corporation
发明人： Gilbert Neiger , Rajesh Sankaran , Gideon Gerzon , Richard Uhlig , Sergiu Ghetie , Michael Neve de Mevergnies , Adil Karrar
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
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2.发明申请公开(公告)号：US20180004595A1
公开(公告)日：2018-01-04
申请号：US15201438
申请日：2016-07-02
申请人： Intel Corporation
发明人： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
IPC分类号： G06F11/10 , G06F12/0893 , G06F12/1045 , G06F12/0875 , G06F3/06
CPC分类号： G06F11/1048 , G06F11/0721
摘要： A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US20230342156A1
公开(公告)日：2023-10-26
申请号：US18138591
申请日：2023-04-24
申请人： Intel Corporation
发明人： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
CPC分类号： G06F9/3844 , G06F9/30101
摘要： Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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公开(公告)号：US20180129619A1
公开(公告)日：2018-05-10
申请号：US15865430
申请日：2018-01-09
申请人： Intel Corporation
发明人： Gilbert Neiger , Rajesh Sankaran , Gideon Gerzon , Richard Uhlig , Sergiu Ghetie , Michael Neve de Mevergnies , Adil Karrar
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
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公开(公告)号：US11068339B2
公开(公告)日：2021-07-20
申请号：US16417555
申请日：2019-05-20
申请人： Intel Corporation
发明人： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
摘要： A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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6.发明申请公开(公告)号：US20190272214A1
公开(公告)日：2019-09-05
申请号：US16417555
申请日：2019-05-20
申请人： Intel Corporation
发明人： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
摘要： A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US10296416B2
公开(公告)日：2019-05-21
申请号：US15201438
申请日：2016-07-02
申请人： Intel Corporation
发明人： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
摘要： A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US20240296051A1
公开(公告)日：2024-09-05
申请号：US18661103
申请日：2024-05-10
申请人： Intel Corporation
发明人： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
CPC分类号： G06F9/3844 , G06F9/30101 , G06F9/3806
摘要： Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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