公开(公告)号：US20230153168A1

公开(公告)日：2023-05-18

申请号：US17455583

申请日：2021-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent ABALI ,  Alper BUYUKTOSUNOGLU ,  Cedric LICHTENAU

IPC: G06F9/50 ,  G06F9/38 ,  H04L9/32 ,  H04L9/08

CPC classification number: G06F9/5072 ,  G06F9/505 ,  G06F9/3877 ,  H04L9/3236 ,  H04L9/0819

Abstract: Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

公开(公告)号：US20210234841A1

公开(公告)日：2021-07-29

申请号：US16751464

申请日：2020-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent ABALI ,  Guerney D. H. HUNT ,  Paul Gregory CRUMLEY

IPC: H04L29/06 ,  H04L12/58

Abstract: Various embodiments are provided for securing data compression in a computer environment are presented. Encryption cycles of a data compression stream may be optimized by applying a first type of encryption on a first section and a last section of compressed data and a second type of encryption on a middle section of compressed data, the first type of encryption containing key information relating to the middle section of the compressed data.

公开(公告)号：US20210165580A1

公开(公告)日：2021-06-03

申请号：US16702080

申请日：2019-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent ABALI ,  Alper BUYUKTOSUNOGLU ,  Balaram SINHAROY

IPC: G06F3/06 ,  G06F12/0891

Abstract: Various embodiments are provided for providing a dynamic random-access memory (“DRAM”) cache as second type memory in a computing system by a processor. A selected amount of bytes in a memory line may be cleared using one or more spare bits of the DRAM, a data compression operation, or a combination thereof. A cache directory and data may be stored in the memory line. The DRAM cache is configured as a cache of a second type memory.

公开(公告)号：US20200183620A1

公开(公告)日：2020-06-11

申请号：US16210708

申请日：2018-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prashant NAIR ,  Seokin HONG ,  Michael HEALY ,  Bulent ABALI ,  Alper BUYUKTOSUNOGLU

IPC: G06F3/06

Abstract: Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.