公开(公告)号：US10019262B2

公开(公告)日：2018-07-10

申请号：US14977782

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Ashish Jha ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark J. Charney ,  Milind B. Girkar

IPC: G06F9/30 ,  G06F9/345

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3455

Abstract: A processor comprises a plurality of vector registers, and an execution unit, operatively coupled to the plurality of vector registers, the execution unit comprising a logic circuit implementing a load instruction for loading, into two or more vector registers, two or more data items associated with a data structure stored in a memory, wherein each one of the two or more vector registers is to store a data item associated with a certain position number within the data structure.