公开(公告)号：US11526483B2

公开(公告)日：2022-12-13

申请号：US15941262

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Stijn Eyerman ,  Jason M. Howard ,  Ibrahim Hur ,  Ivan B. Ganev ,  Fabrizio Petrini ,  Joshua B. Fryman

IPC: G06F16/00 ,  G06F16/22 ,  G06F16/901

Abstract: Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.

公开(公告)号：US10476492B2

公开(公告)日：2019-11-12

申请号：US16201915

申请日：2018-11-27

Applicant: Intel Corporation

Inventor： Ankit More ,  Jason M. Howard ,  Robert Pawlowski ,  Fabrizio Petrini ,  Shaden Smith

IPC: H03K17/00 ,  G11C7/10 ,  H03K19/173

Abstract: Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

公开(公告)号：US20190042613A1

公开(公告)日：2019-02-07

申请号：US15941262

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Stijn Eyerman ,  Jason M. Howard ,  Ibrahim Hur ,  Ivan B. Ganev ,  Fabrizio Petrini ,  Joshua B. Fryman

IPC: G06F17/30

Abstract: Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.