公开(公告)号：US20230056699A1

公开(公告)日：2023-02-23

申请号：US17409090

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F15/78 ,  G06F9/38

Abstract: Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220413860A1

公开(公告)日：2022-12-29

申请号：US17358098

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes: a plurality of registers; a front end circuit to fetch and decode a non-serializing register write instruction, the non-serializing register write instruction to cause a value to be stored in a first register of the plurality of registers; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the non-serializing register write instruction, is to determine an amount of serialization for the non-serializing register write instruction and execute the non-serializing register write instruction according to the amount of serialization. Other embodiments are described and claimed.