公开(公告)号：US20230056699A1

公开(公告)日：2023-02-23

申请号：US17409090

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F15/78 ,  G06F9/38

Abstract: Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US12235791B2

公开(公告)日：2025-02-25

申请号：US17409090

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F9/38 ,  G06F9/32 ,  G06F15/78

Abstract: Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230057623A1

公开(公告)日：2023-02-23

申请号：US17409062

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F15/78 ,  G06F9/38

Abstract: Methods and apparatus relating to issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input, and generates one or more outputs based at least in part on the static input and the dynamic input. The DTL circuitry generates the one or more outputs prior to commencement of speculation operations in a processor. Other embodiments are also disclosed and claimed.