公开(公告)号：US20200107046A1

公开(公告)日：2020-04-02

申请号：US16593710

申请日：2019-10-04

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/14 ,  H04N19/176 ,  H04N19/44 ,  H04N19/136 ,  H04N19/86 ,  H04N19/117

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US10440395B2

公开(公告)日：2019-10-08

申请号：US15271152

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/86 ,  H04N19/80 ,  H04N19/117 ,  H04N19/136 ,  H04N19/44 ,  H04N19/176 ,  H04N19/14 ,  H04N19/172 ,  H04N19/182 ,  H04W84/18

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.