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公开(公告)号：US20230134137A1
公开(公告)日：2023-05-04
申请号：US18090310
申请日：2022-12-28
Applicant: INTEL CORPORATION
Inventor： Jorge E. Caviedes , Mahesh M. Subedar , Khasim S. Dudekula
IPC: H04N19/80 , H04N19/117 , H04N19/86 , H04N19/136 , H04N19/44 , H04N19/176 , H04N19/14
Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
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公开(公告)号：US10863204B2
公开(公告)日：2020-12-08
申请号：US16593710
申请日：2019-10-04
Applicant: INTEL CORPORATION
Inventor： Jorge E. Caviedes , Mahesh M. Subedar , Khasim S. Dudekula
IPC: H04N19/80 , H04N19/117 , H04N19/86 , H04N19/136 , H04N19/44 , H04N19/176 , H04N19/14 , H04N19/172 , H04N19/182 , H04W84/18
Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
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公开(公告)号：US09621741B2
公开(公告)日：2017-04-11
申请号：US14566226
申请日：2014-12-10
Applicant: Intel Corporation
Inventor： Jorge E. Caviedes , Sin Lin Wu , Artem Zinevich , Frank Ghenassia , Dmitri Bitouk
CPC classification number: H04N1/00204 , H04N5/23229 , H04N5/23241
Abstract: Techniques are disclosed to adaptively control an image sensor and image signal processor (ISP), collectively known as an image pipeline, such that a minimum amount of power is consumed by an electronic device while producing images that can be accurately analyzed by a computer vision application. The techniques disclosed herein can be implemented in various electronic devices capable of capturing and processing image data, such as, for example, smart phones, wearable computers, laptops, tablets, and other mobile computing or imaging systems. In an embodiment, the techniques disclosed herein are implemented in a system-on-chip device.
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4.发明申请公开(公告)号：US20150235348A1
公开(公告)日：2015-08-20
申请号：US14704116
申请日：2015-05-05
Applicant: Intel Corporation
Inventor： Abhijit Sarkar , Jorge E. Caviedes , Mahesh Subedar
CPC classification number: G06T5/00 , G06T5/003 , G06T5/007 , G06T2207/10016 , G06T2207/10024 , H04N1/6005 , H04N1/6027 , H04N1/608
Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
Abstract translation: 在一些实施例中，可以一次进行颜色和对比度增强视频处理，而不是调整颜色和对比度增强之一，然后调整另一个，然后返回到第一个以由于第二调整而重新调整。 在一些实施例中，可以同时并行地进行全局亮度调整，局部对比度增强和饱和度增强。 亮度调整提高了一般黑暗或一般较轻的图像的细节的可视性，而不改变原始照片中的预期照明条件，并且用于增强色彩/饱和度增强的范围。 并行的局部对比度增强可以提高对象和纹理的视觉定义，从而提高局部对比度和感知锐度。
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公开(公告)号：US11172233B2
公开(公告)日：2021-11-09
申请号：US17037279
申请日：2020-09-29
Applicant: INTEL CORPORATION
Inventor： Jorge E. Caviedes , Mahesh M. Subedar , Khasim S. Dudekula
IPC: H04N19/80 , H04N19/117 , H04N19/86 , H04N19/136 , H04N19/44 , H04N19/176 , H04N19/14 , H04N19/172 , H04N19/182 , H04W84/18
Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09940543B2
公开(公告)日：2018-04-10
申请号：US15452583
申请日：2017-03-07
Applicant: Intel Corporation
Inventor： Jorge E. Caviedes , Sin Lin Wu
CPC classification number: G06K9/6215 , G06F17/30259 , G06F17/30271 , G06F17/3028 , G06K9/00624 , G06K9/2036 , G06K9/6201 , G06K9/6202 , G06K9/6262
Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
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7.发明授权公开(公告)号：US09560382B2
公开(公告)日：2017-01-31
申请号：US14563017
申请日：2014-12-08
Applicant: Intel Corporation
Inventor： Jorge E. Caviedes , Mahesh M. Subedar , Khasim S. Dudekula
IPC: H04N19/80 , H04N19/176 , H04N19/117 , H04N19/86 , H04N19/136 , H04N19/44
CPC classification number: H04N19/80 , H04N19/117 , H04N19/136 , H04N19/14 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/86 , H04W84/18
Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
Abstract translation: 公开了用于自动减少块编码视频中的块伪影的装置，系统和方法。 在一个实现中，系统包括至少能够至少部分地基于边缘信息和纹理信息来对视频数据行的至少一部分进行去块滤波的处理逻辑，以生成解锁视频行的至少一部分 数据和响应于处理逻辑的图像数据输出装置。
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8.发明申请CONTROL OF COMPUTER VISION PRE-PROCESSING BASED ON IMAGE MATCHING USING STRUCTURAL SIMILARITY 有权使用结构相似性的基于图像匹配的计算机视觉预处理控制公开(公告)号：US20160275369A1
公开(公告)日：2016-09-22
申请号：US14663242
申请日：2015-03-19
Applicant: Intel Corporation
Inventor： Jorge E. Caviedes , Sin Lin Wu
CPC classification number: G06K9/6215 , G06F17/30259 , G06F17/30271 , G06F17/3028 , G06K9/00624 , G06K9/2036 , G06K9/6201 , G06K9/6202 , G06K9/6262
Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
Abstract translation: 处理器计算输入图像的输入图像结构复杂度的度量，并且搜索数据库中的真实肯定值以找到数据库中的一个或多个表示与输入图像结构相似的真正图像的条目。 处理器将输入图像的信号质量的度量与从数据库检索的真正的正像之一的信号质量的度量进行比较，并且基于比较来更新配置信号质量调节过程的控制变量 在由计算机视觉处理器处理输入图像之前对输入图像执行，从而提高计算机视觉任务的性能。 还描述和要求保护其他实施例。
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9.发明授权公开(公告)号：US09053523B2
公开(公告)日：2015-06-09
申请号：US13923451
申请日：2013-06-21
Applicant: Intel Corporation
Inventor： Abhijit Sarkar , Jorge E. Caviedes , Mahesh Subedar
CPC classification number: G06T5/00 , G06T5/003 , G06T5/007 , G06T2207/10016 , G06T2207/10024 , H04N1/6005 , H04N1/6027 , H04N1/608
Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
Abstract translation: 在一些实施例中，可以一次进行颜色和对比度增强视频处理，而不是调整颜色和对比度增强之一，然后调整另一个，然后返回到第一个以由于第二调整而重新调整。 在一些实施例中，可以同时并行地进行全局亮度调整，局部对比度增强和饱和度增强。 亮度调整提高了一般黑暗或一般较轻的图像的细节的可视性，而不改变原始照片中的预期照明条件，并且用于增强色彩/饱和度增强的范围。 并行的局部对比度增强可以提高对象和纹理的视觉定义，从而提高局部对比度和感知锐度。
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公开(公告)号：US20150092866A1
公开(公告)日：2015-04-02
申请号：US14563017
申请日：2014-12-08
Applicant: Intel Corporation
Inventor： Jorge E. Caviedes , Mahesh Subedar , Khasim S. Kudekula
IPC: H04N19/80 , H04N19/117 , H04N19/176
CPC classification number: H04N19/80 , H04N19/117 , H04N19/136 , H04N19/14 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/86 , H04W84/18
Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
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