公开(公告)号：US20220197798A1

公开(公告)日：2022-06-23

申请号：US17130679

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu JIndal ,  Leon Polishuk ,  Yossi Grotas

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0831 ,  G06F12/02

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify single re-use data evicted from a core cache, and retain the identified single re-use data in a next level cache based on an overall re-use of the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US10229059B2

公开(公告)日：2019-03-12

申请号：US15476816

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Eran Shifer ,  Leon Polishuk

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/1027 ,  G06F3/06 ,  G06F9/455

Abstract: Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

公开(公告)号：US20180095883A1

公开(公告)日：2018-04-05

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F12/0866 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.