公开(公告)号：US20220197797A1

公开(公告)日：2022-06-23

申请号：US17130676

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0815

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US20180203799A1

公开(公告)日：2018-07-19

申请号：US15408731

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant Nori ,  Sreenivas Subramoney

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F11/34 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/502

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US12130739B2

公开(公告)日：2024-10-29

申请号：US16833304

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F12/123 ,  G06F2212/1021

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20230305960A1

公开(公告)日：2023-09-28

申请号：US17705015

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Oz Shitrit ,  Elyada Bar-Chaim ,  Mauricio Valverde Monge ,  Ayan Mandal

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

公开(公告)号：US20210303467A1

公开(公告)日：2021-09-30

申请号：US16833304

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu Jindal ,  Leon Polishuk ,  Yossi Grotas ,  Aravindh Anantaraman

IPC: G06F12/0811 ,  G06F12/0831 ,  G06F12/123

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

公开(公告)号：US20190243760A1

公开(公告)日：2019-08-08

申请号：US16222788

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant V. Nori ,  Sreenivas Subramoney

IPC: G06F12/0811 ,  G06F12/0888 ,  G06F12/0804 ,  G06F12/084 ,  G06F11/34

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US20180285261A1

公开(公告)日：2018-10-04

申请号：US15476816

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Eran Shifer ,  Leon Polishuk

IPC: G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/1027 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0653 ,  G06F9/5016 ,  G06F12/0223 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/604 ,  G06F2212/6046

Abstract: Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

公开(公告)号：US12111762B2

公开(公告)日：2024-10-08

申请号：US17130676

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

IPC: G06F3/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F2212/1032

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US20240220410A1

公开(公告)日：2024-07-04

申请号：US18089757

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Prasanna Pandit ,  Neetu Jindal ,  Israel Diamand ,  Asaf Rubinstein ,  Leon Polishuk ,  Oz Shitrit

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/62

Abstract: Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220197798A1

公开(公告)日：2022-06-23

申请号：US17130679

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Neetu JIndal ,  Leon Polishuk ,  Yossi Grotas

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0831 ,  G06F12/02

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify single re-use data evicted from a core cache, and retain the identified single re-use data in a next level cache based on an overall re-use of the next level cache. Other embodiments are disclosed and claimed.