公开(公告)号：US20240088253A1

公开(公告)日：2024-03-14

申请号：US18510402

申请日：2023-11-15

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Ting CHANG ,  Nidhi NIDHI ,  Walid M. HAFEZ

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US20220359697A1

公开(公告)日：2022-11-10

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Ting CHANG ,  Nidhi NIDHI ,  Walid M. HAFEZ

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US20210193844A1

公开(公告)日：2021-06-24

申请号：US16725161

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Babak FALLAHAZAD ,  Hsiao-Yuan WANG ,  Ting CHANG ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Nidhi NIDHI ,  Walid M. HAFEZ

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a source, a drain, and a semiconductor channel between the source and the drain. In an embodiment, the semiconductor channel has a non-uniform strain through a thickness of the semiconductor channel. In an embodiment, the semiconductor device further comprises a gate stack around the semiconductor channel.

公开(公告)号：US20210184032A1

公开(公告)日：2021-06-17

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi NIDHI ,  Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Ting CHANG ,  Babak FALLAHAZAD ,  Tanuj TRIVEDI ,  Jeong Dong KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US20210184000A1

公开(公告)日：2021-06-17

申请号：US16713670

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ting CHANG ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

公开(公告)号：US20210183850A1

公开(公告)日：2021-06-17

申请号：US16713656

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi NIDHI ,  Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Ting CHANG ,  Babak FALLAHAZAD ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ayan KAR ,  Benjamin ORR

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.