公开(公告)号：US4308501A

公开(公告)日：1981-12-29

申请号：US621706

申请日：1975-10-09

申请人： Thomas E. Tuccinardi ,  Michael Conner

发明人： Thomas E. Tuccinardi ,  Michael Conner

IPC分类号： F42C11/00 ,  F42C13/08 ,  G01P3/52 ,  H03K5/153

CPC分类号： F42C13/08 ,  F42C11/007 ,  G01P3/52

摘要： A digital circuit for sensing peaks exceeding a predetermined threshold innalog signals employs clock and control oscillators arranged such that their frequencies vary in opposite senses in response to changes in the sensed signal. The clock oscillator frequency is counted during sample intervals of durations which vary inversely with the control oscillator frequency. A count increase (or decrease) of predetermined amount from one sample interval to the next, followed by a count decrease (or increase) from another sample interval to the next, results in an output signal. In a preferred embodiment, the clock frequency is counted in an up/down counter which, for each sample interval, is counted up and down for equal numbers of control oscillator cycles. The net count at the end of a sample interval is therefore an indication of the magnitude and polarity of changes in the sensed signal. In a particular utilization the circuit serves in a mine fuze and senses the peak of a magnetic field signal such as is associated with a tank or other vehicle.

摘要翻译： 用于在模拟信号中感测超过预定阈值的峰值的数字电路采用时钟和控制振荡器，其布置成使得它们的频率响应于感测信号的变化而以相反的方式变化。 在与控制振荡器频率反向变化的持续时间的采样间隔期间对时钟振荡器频率进行计数。 从一个采样间隔到下一个采样间隔的计数增加（或减小），随后从另一个采样间隔到下一个采样间隔的计数减小（或增加）导致输出信号。 在优选实施例中，时钟频率在升/降计数器中计数，对于每个采样间隔，对于相等数量的控制振荡器周期，上下计数。 因此，采样间隔结束时的净计数表示感测信号的变化的大小和极性。 在一个特定的利用中，该电路用于矿井引信，并且感测与罐或其他车辆相关联的磁场信号的峰值。