公开(公告)号：US07024536B2

公开(公告)日：2006-04-04

申请号：US10253408

申请日：2002-09-24

申请人： Sang-hyun Park ,  Seh-Woong Jeong ,  Shin-dug Kim ,  Jung-Hoon Lee

发明人： Sang-hyun Park ,  Seh-Woong Jeong ,  Shin-dug Kim ,  Jung-Hoon Lee

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/1028 ,  G06F2212/652 ,  G06F2212/681 ,  Y02D10/13

摘要： A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

摘要翻译： 提供了能够降低功耗并提高存储器性能的翻译后备缓冲器（TLB）。 将虚拟地址转换为物理地址的全关联TLB包括具有多个存储体的第一TLB; 具有多个条目的第二TLB，每个条目具有一个虚拟页码和2个N个物理页号，其中N是自然数; 以及选择电路，用于响应于选择信号将第一TLB的输出信号输出到第二TLB，其中第一TLB的每个存储体具有多个条目，每个条目具有一个虚拟页码和一个物理页码 。 由第一TLB的虚拟页码指示的页面的大小与由第二TLB的虚拟页面编号指示的页面的大小不同。