公开(公告)号：US20240354216A1

公开(公告)日：2024-10-24

申请号：US18577972

申请日：2022-06-10

Applicant: Arm Limited

Inventor： Matthew Lucien Evans ,  Robert Gwilym Dimond ,  Alexander Donald Charles Chadwick

IPC: G06F11/34 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F11/3471 ,  G06F12/1009 ,  G06F12/1027

Abstract: An apparatus comprises: memory access circuitry (11) to process memory access requests requesting access to a memory system (10, 32); and access frequency tracking circuitry (40). In response to a given memory access request requesting access to a given page of a memory address space, the access frequency tracking circuitry (40) determines an outcome of a chance-dependent test, where the outcome of the chance-dependent test is dependent on chance. When the outcome of the chance-dependent test is a first outcome, an access frequency tracking indicator corresponding to the given page is updated within an access frequency tracking structure. When the chance-dependent test has an outcome other than the first outcome. the access frequency tracking circuitry 40 omits updating of the access frequency tracking indicator corresponding to the given page.

公开(公告)号：US12124381B2

公开(公告)日：2024-10-22

申请号：US17529499

申请日：2021-11-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang

IPC: G06F12/10 ,  G06F12/1027 ,  G06F8/41

CPC classification number: G06F12/1027 ,  G06F8/44 ,  G06F2212/651 ,  G06F2212/68

Abstract: A processing system includes a hardware translation lookaside buffer (TLB) retry loop that retries virtual memory address to physical memory address translation requests from a software client independent of a command from the software client. In response to a retry response notification at the TLB, a controller of the TLB waits for a programmable delay period and then retries the request without involvement from the software client. After a retry results in a hit at the TLB, the controller notifies the software client of the hit. Alternatively, if a retry results in an error at the TLB, the controller notifies the software client of the error and the software client initiates error handling.

公开(公告)号：US20240320157A1

公开(公告)日：2024-09-26

申请号：US18188200

申请日：2023-03-22

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/1027

Abstract: Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

公开(公告)号：US12099450B1

公开(公告)日：2024-09-24

申请号：US18312735

申请日：2023-05-05

Applicant: Arm Limited

Inventor： Richard Jared Cooper ,  Andreas Lars Sandberg

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: Address translation circuitry is provided to perform address translation on receipt of a first address to generate a second address. The address translation circuitry comprises a page walk controller configured to perform sequential page table lookups in a plurality of page table levels of a page table hierarchy. Portions of the first address are used to index into sequential page table levels. Cache storage is provided to cache entries comprising translation information retrieved by the sequential page table lookups. An entry in the cache storage further comprises in association with the translation information a re-use indicator indicative of a re-use expectation for subsequent information which is subordinate to the translation information of the entry in the page table hierarchy. The address translation circuitry is configured to modify cache usage for the subsequent information in dependence on the re-use indicator.

公开(公告)号：US20240296128A1

公开(公告)日：2024-09-05

申请号：US18116543

申请日：2023-03-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Sheng

IPC: G06F12/1027 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1027 ,  G06F12/0292 ,  G06F13/1626

Abstract: An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.

公开(公告)号：US20240289280A1

公开(公告)日：2024-08-29

申请号：US18432617

申请日：2024-02-05

Applicant: Rockwell Collins, Inc.

Inventor： John M. Connelly ,  Nisar Ahemad Naikwadi ,  Joseph A. Steffen

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009

Abstract: A microprocessor is described. The microprocessor includes a software-based monitor for detecting TLB corruptions. The TLB corruptions contribute to undetected erroneous upset rate of the microprocessor. The software monitor detects errors in the TLB. The software-based monitor detects TLB corruptions in microprocessors where hardware protection mechanisms are not available. The software monitor mitigates single event effects due to atmospheric particles and improves the safety of high integrity computing products.

公开(公告)号：US20240281382A1

公开(公告)日：2024-08-22

申请号：US18235365

申请日：2023-08-18

Applicant: MEDIATEK INC.

Inventor： En-Shou Tang ,  Yuan-Chun Lin ,  Kai-Hsiang Chang ,  Yi-Che Tsai

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F13/1689

Abstract: A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.

公开(公告)号：US12032487B2

公开(公告)日：2024-07-09

申请号：US17666974

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Michael Mantor

IPC: G06F12/10 ,  G06F12/0893 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20240211410A1

公开(公告)日：2024-06-27

申请号：US18500781

申请日：2023-11-02

Applicant: Rebellions Inc.

Inventor： Chang-Hyo Yu

IPC: G06F12/1027 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06F12/1027 ,  G06N3/04 ,  G06N3/08

Abstract: A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.

公开(公告)号：US20240211401A1

公开(公告)日：2024-06-27

申请号：US18522776

申请日：2023-11-29

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Young-Su KWON

IPC: G06F12/0815 ,  G06F12/1027

CPC classification number: G06F12/0815 ,  G06F12/1027

Abstract: Disclosed herein are a method for supporting cache coherency based on virtual addresses for an artificial intelligence processor having large on-chip memory and an apparatus for the same. The method for supporting cache coherency according to an embodiment of the present disclosure includes, by an artificial intelligence processor including multiple processor cores and multiple caches, setting external memory address areas which do not overlap each other for respective multiple caches; and providing virtual addresses with which the multiple processor cores access the multiple caches.