公开(公告)号：US20070226424A1

公开(公告)日：2007-09-27

申请号：US11388013

申请日：2006-03-23

申请人： Scott Clark ,  Andrew Wottreng

发明人： Scott Clark ,  Andrew Wottreng

IPC分类号： G06F13/28

CPC分类号： G06F12/0817 ,  G06F2212/1016

摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

摘要翻译： 本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。