公开(公告)号：US12066944B2

公开(公告)日：2024-08-20

申请号：US16723780

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Amit P. Apte

IPC: G06F12/0815 ,  G06F12/0817 ,  G06F12/0888 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0817 ,  G06F12/0888 ,  G06F12/0891 ,  G06F2212/608

Abstract: A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If the entry exists in the cache directory, is invalid, and includes an indication that data corresponding to the memory address includes zero data, the coherency management device returns zero data in response to the request without fetching the data from main memory or a cache.

公开(公告)号：US11775171B2

公开(公告)日：2023-10-03

申请号：US17403468

申请日：2021-08-16

Applicant: Ultrata, LLC

Inventor： Steven J. Frank ,  Larry Reback

IPC: G06F3/06 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/0877

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/064 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0635 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/0877 ,  G06F2212/2542 ,  G06F2212/6012

Abstract: Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

公开(公告)号：US20230222066A1

公开(公告)日：2023-07-13

申请号：US17572245

申请日：2022-01-10

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Naga P. Gorti ,  Guy L. Guthrie ,  Sanjeev Ghai

IPC: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804

CPC classification number: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804 ,  G06F2212/1021

Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

公开(公告)号：US11698816B2

公开(公告)日：2023-07-11

申请号：US17008549

申请日：2020-08-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Matthew S. Gates ,  Joel E. Lilienkamp ,  Alex Veprinsky ,  Susan Agten

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0817

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06F9/544 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/1024 ,  G06F2212/2542

Abstract: Systems and methods are provided for lock-free thread scheduling. Threads may be placed in a ring buffer shared by all computer processing units (CPUs), e.g., in a node. A thread assigned to a CPU may be placed in the CPU's local run queue. However, when a CPU's local run queue is cleared, that CPU checks the shared ring buffer to determine if any threads are waiting to run on that CPU, and if so, the CPU pulls a batch of threads related to that ready-to-run thread to execute. If not, an idle CPU randomly selects another CPU to steal threads from, and the idle CPU attempts to dequeue a thread batch associated with the CPU from the shared ring buffer. Polling may be handled through the use of a shared poller array to dynamically distribute polling across multiple CPUs.

公开(公告)号：US11687459B2

公开(公告)日：2023-06-27

申请号：US17230286

申请日：2021-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US11669454B2

公开(公告)日：2023-06-06

申请号：US16405691

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Jeffrey Baxter ,  Sai Prashanth Muralidhara ,  Sharada Venkateswaran ,  Daniel Liu ,  Nishant Singh ,  Bahaa Fahim ,  Samuel D. Strom

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

公开(公告)号：US11656992B2

公开(公告)日：2023-05-23

申请号：US16548116

申请日：2019-08-22

Applicant: Western Digital Technologies, Inc.

Inventor： Marjan Radi ,  Dejan Vucinic

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0806 ,  G06F12/0802 ,  H04L67/1097 ,  G06F12/0817 ,  H04L67/568 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F12/082 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0828 ,  H04L67/1097 ,  H04L67/568 ,  G06F9/34 ,  G06F9/3824 ,  G06F2212/154 ,  G06F2212/602

Abstract: A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.

公开(公告)号：US20190220408A1

公开(公告)日：2019-07-18

申请号：US15873515

申请日：2018-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ERIC E. RETTER ,  MICHAEL S. SIEGEL ,  JEFFREY A. STUECHELI ,  DEREK E. WILLIAMS

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0833

Abstract: A data processing system includes first and second coherency domains and employs a snoop-based coherence protocol. In response to receipt by the first coherency domain of a memory access request originating from a master in the second coherency domain, a plurality of coherence participants in the first coherency domain provides partial responses for the memory access request to an early combined response generator. Based on the partial responses, the early combined response generator generates and transmits, to a memory controller of a system memory in the first coherency domain, an early combined response of only the first coherency domain. Based on the early combined response, the memory controller transmits, to the master prior to receipt by the memory controller of a systemwide combined response for the memory access request, data associated with a target memory address and/or coherence permission for the target memory address.

公开(公告)号：US20180307604A1

公开(公告)日：2018-10-25

申请号：US15495145

申请日：2017-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F12/0817 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F2212/60 ,  G06F2212/621

Abstract: Methods and systems for memory-side shared caching include determining whether a requested memory access is directed to shared portion of memory by referencing a lock address list in a memory controller. If the requested memory access is for the shared portion of memory, it is determined whether an associated data object is present in a memory-side cache. If the associated data object is present in the memory-side cache, the memory-side cache is accessed. If the associated data object is not present in the memory-side cache, an external memory is accessed.

公开(公告)号：US20180217933A1

公开(公告)日：2018-08-02

申请号：US15747755

申请日：2015-07-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan SHERLOCK ,  Shawn WALKER

IPC: G06F12/0862 ,  G06F12/0873 ,  G06F12/0804 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0891

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0873 ,  G06F12/0891

Abstract: An apparatus for assisting a flush of a cache is described herein. The apparatus comprises processing element. The processing element is to probe a cache line at an offset address and write the cache line at the offset address to a non-volatile memory in response to a flush instruction at a first address.