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公开(公告)号：US07061337B2
公开(公告)日：2006-06-13
申请号：US10890764
申请日：2004-07-14
CPC分类号： H03L5/00 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B2200/0038
摘要： An amplitude control circuit comprises a first circuit configured to receive differential signals and provide a first signal based on the amplitudes of the differential signals, a second circuit configured to receive a bias signal and provide a second signal based on the bias signal, and a third circuit configured to provide bias to the first circuit and the bias signal to the second circuit. The bias signal is set to provide selected amplitudes of the differential signals.
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公开(公告)号：US20060012447A1
公开(公告)日：2006-01-19
申请号：US10890764
申请日：2004-07-14
IPC分类号： H03L7/099
CPC分类号： H03L5/00 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B2200/0038
摘要： An amplitude control circuit comprises a first circuit configured to receive differential signals and provide a first signal based on the amplitudes of the differential signals, a second circuit configured to receive a bias signal and provide a second signal based on the bias signal, and a third circuit configured to provide bias to the first circuit and the bias signal to the second circuit. The bias signal is set to provide selected amplitudes of the differential signals.
摘要翻译： 振幅控制电路包括被配置为接收差分信号并基于差分信号的幅度提供第一信号的第一电路，被配置为接收偏置信号并基于偏置信号提供第二信号的第二电路，以及第三电路 电路，被配置为向第一电路提供偏置并将偏置信号提供给第二电路。 偏置信号被设置为提供差分信号的选定幅度。
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13.发明授权公开(公告)号：US07902876B2
公开(公告)日：2011-03-08
申请号：US12058671
申请日：2008-03-29
IPC分类号： H03K19/00
摘要： In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del1, Cnt_del2). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal. The output signal is formed from the at least one first data signal, whereby the outputting is carried out edge-synchronously to the first and the second clock signal.
摘要翻译： 在一个实施例中，本发明涉及一种集成电路，其包括至少一个数据信号输入（data1，data2），至少一个时钟信号输入（Clock），至少一个控制信号输入（Cnt_del1，Cnt_del2）和数据信号 输出（Data_out）。 根据本发明，集成电路被配置为在其输出（Data_out）处提供具有可变符号持续时间的数字数据信号，该符号持续时间可通过控制信号（Cnt_del1，Cnt_del2）来控制。 本发明的另一实施例涉及一种用于产生具有可变符号持续时间的数字数据信号的方法，其中输出信号由至少一个第一数据信号，至少一个第一时钟信号和至少一个控制信号产生。 为此，从第一时钟信号产生至少一个第二时钟信号，第二时钟信号具有可变延迟，并且根据至少一个控制信号的值来设置延迟。 输出信号由至少一个第一数据信号形成，从而与第一和第二时钟信号同步地执行输出。
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14.发明申请公开(公告)号：US20090243684A1
公开(公告)日：2009-10-01
申请号：US12058671
申请日：2008-03-29
IPC分类号： H03K5/04
摘要： In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del1, Cnt_del2). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal. The output signal is formed from the at least one first data signal, whereby the outputting is carried out edge-synchronously to the first and the second clock signal.
摘要翻译： 在一个实施例中，本发明涉及一种集成电路，其包括至少一个数据信号输入（data1，data2），至少一个时钟信号输入（Clock），至少一个控制信号输入（Cnt_del1，Cnt_del2）和数据信号 输出（Data_out）。 根据本发明，集成电路被配置为在其输出（Data_out）处提供具有可变符号持续时间的数字数据信号，该符号持续时间可通过控制信号（Cnt_del1，Cnt_del2）来控制。 本发明的另一实施例涉及一种用于产生具有可变符号持续时间的数字数据信号的方法，其中输出信号由至少一个第一数据信号，至少一个第一时钟信号和至少一个控制信号产生。 为此，从第一时钟信号产生至少一个第二时钟信号，第二时钟信号具有可变延迟，并且根据至少一个控制信号的值来设置延迟。 输出信号由至少一个第一数据信号形成，从而与第一和第二时钟信号同步地执行输出。
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公开(公告)号：US20110059316A1
公开(公告)日：2011-03-10
申请号：US12789025
申请日：2010-05-27
申请人： Srinivas Kilambi , Krishnan Iyer , Karthik Gopalakrishnan , Ramesh Chembeti , Niraj Singh , Satish Reddy Dhumpala , Zijun Liu , Raman Kumar Gottumukkala , Subhadeep Mukherjee
发明人： Srinivas Kilambi , Krishnan Iyer , Karthik Gopalakrishnan , Ramesh Chembeti , Niraj Singh , Satish Reddy Dhumpala , Zijun Liu , Raman Kumar Gottumukkala , Subhadeep Mukherjee
CPC分类号： C04B7/425 , C04B7/364 , C04B2111/802 , Y02P40/121 , Y02P40/18 , Y10T428/2982 , C04B7/361
摘要： A method of making cementitious particles using combustion synthesis is described. The method uses less energy and produces lower CO2 emissions than conventional processes. By controlling the process conditions, the morphology and the properties of the particles can be easily tuned for a variety of applications. A batch reactor and a continuous conveyor type reactor that can be used for the combustion synthesis with high viscosity raw materials are also described.
摘要翻译： 描述了使用燃烧合成制造水泥质颗粒的方法。 该方法比常规方法使用更少的能量并产生较低的二氧化碳排放。 通过控制工艺条件，可以容易地调整颗粒的形态和性质用于各种应用。 还描述了可用于用高粘度原料进行燃烧合成的间歇式反应器和连续传送式反应器。
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公开(公告)号：US08500902B2
公开(公告)日：2013-08-06
申请号：US12789025
申请日：2010-05-27
申请人： Srinivas Kilambi , Krishnan Iyer , Karthik Gopalakrishnan , Ramesh Chembeti , Niraj Singh , Satish Reddy Dhumpala , Zijun Liu , Raman Kumar Gottumukkala , Subhadeep Mukherjee
发明人： Srinivas Kilambi , Krishnan Iyer , Karthik Gopalakrishnan , Ramesh Chembeti , Niraj Singh , Satish Reddy Dhumpala , Zijun Liu , Raman Kumar Gottumukkala , Subhadeep Mukherjee
IPC分类号： C04B7/43
CPC分类号： C04B7/425 , C04B7/364 , C04B2111/802 , Y02P40/121 , Y02P40/18 , Y10T428/2982 , C04B7/361
摘要： A method of making cementitious particles using combustion synthesis is described. The method uses less energy and produces lower CO2 emissions than conventional processes. By controlling the process conditions, the morphology and the properties of the particles can be easily tuned for a variety of applications. A batch reactor and a continuous conveyor type reactor that can be used for the combustion synthesis with high viscosity raw materials are also described.
摘要翻译： 描述了使用燃烧合成制造水泥质颗粒的方法。 该方法比常规方法使用更少的能量并产生较低的二氧化碳排放。 通过控制工艺条件，可以容易地调整颗粒的形态和性质用于各种应用。 还描述了可用于用高粘度原料进行燃烧合成的间歇式反应器和连续传送式反应器。
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