公开(公告)号：US08141014B2

公开(公告)日：2012-03-20

申请号：US12538229

申请日：2009-08-10

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

公开(公告)号：US07987440B2

公开(公告)日：2011-07-26

申请号：US12351944

申请日：2009-01-12

申请人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

发明人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

摘要翻译： 一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。 分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。 一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。 该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

公开(公告)号：US08775988B2

公开(公告)日：2014-07-08

申请号：US13150445

申请日：2011-06-01

申请人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

发明人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/504 ,  G06F2217/84

摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

摘要翻译： 一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。 本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。 对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

公开(公告)号：US20120311514A1

公开(公告)日：2012-12-06

申请号：US13150445

申请日：2011-06-01

申请人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

发明人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/84

摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

摘要翻译： 一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。 本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。 对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

公开(公告)号：US20080134117A1

公开(公告)日：2008-06-05

申请号：US11565803

申请日：2006-12-01

申请人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

摘要翻译： 一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试 到点延迟约束。 该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。 另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们 是希望的。 最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。 基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

公开(公告)号：US20100318951A1

公开(公告)日：2010-12-16

申请号：US12484293

申请日：2009-06-15

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

摘要翻译： 一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。 该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。 然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。 此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个 基于历史的延迟变异性和时间传播。

公开(公告)号：US07698674B2

公开(公告)日：2010-04-13

申请号：US11565803

申请日：2006-12-01

申请人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

摘要翻译： 一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试 到点延迟约束。 该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。 另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们 是希望的。 最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。 基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

公开(公告)号：US20100180242A1

公开(公告)日：2010-07-15

申请号：US12351944

申请日：2009-01-12

申请人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

发明人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

摘要翻译： 一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。 分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。 一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。 该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

公开(公告)号：US20080250370A1

公开(公告)日：2008-10-09

申请号：US11733058

申请日：2007-04-09

申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

公开(公告)号：US07814448B2

公开(公告)日：2010-10-12

申请号：US11733058

申请日：2007-04-09

申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。