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    Decentralized dynamically scheduled parallel static timing analysis
    1.
    发明授权
    Decentralized dynamically scheduled parallel static timing analysis 失效
    分散式动态调度并行静态时序分析

    公开(公告)号：US08775988B2

    公开(公告)日：2014-07-08

    申请号：US13150445

    申请日：2011-06-01

    申请人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    发明人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/504 ,  G06F2217/84

    摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

    摘要翻译： 一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。 本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。 对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

    Decentralized Dynamically Scheduled Parallel Static Timing Analysis
    2.
    发明申请
    Decentralized Dynamically Scheduled Parallel Static Timing Analysis 失效
    分散式动态调度并行静态时序分析

    公开(公告)号：US20120311514A1

    公开(公告)日：2012-12-06

    申请号：US13150445

    申请日：2011-06-01

    申请人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    发明人： Mark A. Lavin ,  David J. Hathaway ,  Kerim Kalafala ,  Jeffrey S. Piaget ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504 ,  G06F2217/84

    摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

    摘要翻译： 一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。 本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。 对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

    System and method for correlated process pessimism removal for static timing analysis
    4.
    发明授权
    System and method for correlated process pessimism removal for static timing analysis 失效
    静态时序分析相关过程悲观消除的系统和方法

    公开(公告)号：US07117466B2

    公开(公告)日：2006-10-03

    申请号：US10665273

    申请日：2003-09-18

    申请人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

    摘要翻译： 描述了静态时序分析中消除悲观情绪的方法。 延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。 根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。 分析以路径为基础进行。 通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。 此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。 另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

    SYSTEM AND METHOD FOR EFFICIENT ANALYSIS OF POINT-TO-POINT DELAY CONSTRAINTS IN STATIC TIMING
    6.
    发明申请
    SYSTEM AND METHOD FOR EFFICIENT ANALYSIS OF POINT-TO-POINT DELAY CONSTRAINTS IN STATIC TIMING 失效
    点对点延迟约束在静态时序中有效分析的系统与方法

    公开(公告)号：US20080134117A1

    公开(公告)日：2008-06-05

    申请号：US11565803

    申请日：2006-12-01

    申请人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

    摘要翻译： 一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试 到点延迟约束。 该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。 另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们 是希望的。 最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。 基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

    System and method for efficient analysis of point-to-point delay constraints in static timing
    7.
    发明授权
    System and method for efficient analysis of point-to-point delay constraints in static timing 失效
    用于静态时序点对点延迟约束的有效分析的系统和方法

    公开(公告)号：US07698674B2

    公开(公告)日：2010-04-13

    申请号：US11565803

    申请日：2006-12-01

    申请人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

    摘要翻译： 一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试 到点延迟约束。 该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。 另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们 是希望的。 最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。 基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

    Method for performing a parallel static timing analysis using thread-specific sub-graphs
    8.
    发明授权
    Method for performing a parallel static timing analysis using thread-specific sub-graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US08381150B2

    公开(公告)日：2013-02-19

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs
    9.
    发明申请
    Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs 有权
    使用线程特定子图执行并行静态时序分析的方法

    公开(公告)号：US20120311515A1

    公开(公告)日：2012-12-06

    申请号：US13151295

    申请日：2011-06-02

    申请人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    发明人： Vladimir Zolotov ,  David J. Hathaway ,  Kerim Kalafala ,  Mark A. Lavin ,  Peihua Qi

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5031 ,  G06F8/20 ,  G06F2217/84

    摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.

    摘要翻译： 描述了一种用于定时图的有效多线程分析的方法。 该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。 为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。 使用一个父计算线程和多个子线程。 父计算线程识别用于分析的任务，并在子线程之间分配它们。 每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。 完成分析后，子线程将结果传回主时序图，等待下一个任务。 由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。 每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。 访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

    SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS
    10.
    发明申请
    SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS 有权
    系统和方法在静态时序分析期间的共同历史缓解

    公开(公告)号：US20110035714A1

    公开(公告)日：2011-02-10

    申请号：US12538229

    申请日：2009-08-10

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

    摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。