Abstract:
An organic light emitting device including an organic light emitting element having a low driving voltage and a high luminous efficiency is provided. The organic light emitting device includes two or more stack emission units, and a charge generating layer including an N-type charge generating layer and a P-type charge generating layer is disposed between the stack emission units. Herein, the P-type charge generating layer is formed of a material having an LUMO energy level similar to an HOMO energy level of a hole transporting layer injected with holes from the P-type charge generating layer. Accordingly, even if the P-type charge generating layer is not additionally doped with a P-type dopant, it is possible to readily inject holes into a stack emission unit adjacent to the P-type charge generating layer.
Abstract:
Disclosed is an organic light emitting display device. The organic light emitting display device includes a first emission part between a first electrode and a second electrode and a second emission part on the first emission part. The first emission part includes a first hole transport layer and a first emission layer, and the second emission part includes a second hole transport layer and a second emission layer. A thickness of the second hole transport layer is greater than a thickness of the first hole transport layer.
Abstract:
An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.