公开(公告)号：US10777143B2

公开(公告)日：2020-09-15

申请号：US16548761

申请日：2019-08-22

Applicant: LG Display Co., Ltd.

Inventor： Myungho Ban ,  Inhyo Han ,  Seok Noh ,  Kimin Son

IPC: G09G3/3266 ,  G09G3/3233 ,  G09G3/3283 ,  G09G3/3291 ,  G09G3/3258

Abstract: A gate driver includes a gate shift register in which an A block and a B block each having a plurality of stages, the A block and the B block being alternately arranged; scan clock lines inputting a first scan clock group and a second scan clock group each including both image data writing (IDW) scan clocks synchronized with an image write timing and black data insertion (BDI) scan clocks synchronized with a black write timing to the A block and the B block; and carry clock lines inputting carry clocks to the A block and the B block and sense clock lines inputting sense clocks to the A block and the B block, wherein each of the stages belonging to the A block and the B block includes a BDI memory storing a BDI carry signal for outputting the BDI scan clocks.

公开(公告)号：US11955085B2

公开(公告)日：2024-04-09

申请号：US17859947

申请日：2022-07-07

Applicant: LG Display Co., Ltd.

Inventor： Seok Noh ,  Ki Min Son

IPC: G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2320/043 ,  G09G2320/0673 ,  G09G2330/021

Abstract: An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.

公开(公告)号：US11798489B2

公开(公告)日：2023-10-24

申请号：US17859852

申请日：2022-07-07

Applicant: LG Display Co., Ltd.

Inventor： Ki Won Son ,  Seok Noh ,  Ki Min Son ,  Seo Jun Yeom

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0426 ,  G09G2300/0852

Abstract: A gate driver according to an embodiment and a display device using the same are discussed. The gate driver can output a gate signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line and driven by the gate signal. The gate driver includes a first circuit unit to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node, and a second circuit unit having a first buffer transistor and a second buffer transistor configured to output the gate signal based on a first clock signal and a first low potential voltage according to potentials of the first and second control nodes.

公开(公告)号：US20230029234A1

公开(公告)日：2023-01-26

申请号：US17859940

申请日：2022-07-07

Applicant: LG Display Co., Ltd.

Inventor： Ki Min Son ,  Chang Hee Kim ,  Seok Noh

IPC: G09G3/3233 ,  G09G3/3266

Abstract: A pixel circuit comprises a first switch element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which a initialization pulse is applied, and a second electrode connected to a second node; a second switch element comprising a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switch element comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switch element comprising a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node.

公开(公告)号：US20230010366A1

公开(公告)日：2023-01-12

申请号：US17861027

申请日：2022-07-08

Applicant: LG Display Co., Ltd.

Inventor： Ki Won Son ,  Ki Min Son ,  Seok Noh

IPC: G09G3/3291 ,  G09G3/3266

Abstract: The present disclosure is directed to a gate driver circuit configured to prevent a light-emitting element of a display device from emitting light in a sensing mode. The gate driver circuit allows a plurality of scan lines of the display device being concurrently sensed by pre-charging a node of the gate driver circuit prior starting a sensing mode. The present disclosure provides the benefit of sensing a greater number of pixels of a display in a shorter time while also ensuring that a sufficient charge is provided by the pre-charged node for a plurality of pixels of the plurality of scan lines to be sensed concurrently.

公开(公告)号：US11244644B2

公开(公告)日：2022-02-08

申请号：US16599810

申请日：2019-10-11

Applicant: LG Display Co., Ltd.

Inventor： Seok Noh ,  Kyungmin Kim

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266

Abstract: The disclosure provides a shift register including a node controller configured to control charging and discharging of a node Q and a node QB, and an output circuit including a first buffer transistor configured to output a first scan signal, a second buffer transistor configured to output a second scan signal and a third buffer transistor configured to output a carry signal in response to electric potentials of the node Q and the node QB. The first buffer transistor and the second buffer transistor have different channel region widths. The output circuit may further include a first dummy buffer transistor having a common gate and common drain connection structure with the first buffer transistor.

公开(公告)号：US10546520B2

公开(公告)日：2020-01-28

申请号：US16044260

申请日：2018-07-24

Applicant: LG Display Co., Ltd.

Inventor： Seok Noh ,  In-Hyo Han

IPC: G09G3/20 ,  G09G3/36

Abstract: Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.