公开(公告)号：US20220208063A1

公开(公告)日：2022-06-30

申请号：US17556952

申请日：2021-12-20

Applicant: LG Display Co., Ltd.

Inventor： Soon-Hwan Hong ,  Dae-Seok Oh ,  Seong-Yeong Kim

IPC: G09G3/20 ,  G09G3/3225

Abstract: A display device includes: a timing controlling part generating an image data, a data control signal and a gate control signal; a data driving part generating a data voltage using the image data and the data control signal; a gamma part transmitting the data voltage corresponding to the image data; a gate driving part generating a gate voltage using the gate control signal; a display panel including subpixels, gate lines, left data lines at a left side of the subpixels and right data lines at a right side of the subpixels; and first MUX switches, second MUX switches, third MUX switches, fourth MUX switches, fifth MUX switches and sixth MUX switches sequentially transmitting the data voltage to the left data lines and the right data lines.

公开(公告)号：US20220122541A1

公开(公告)日：2022-04-21

申请号：US17506563

申请日：2021-10-20

Applicant: LG Display Co., Ltd.

Inventor： Eui-Hyun Chung ,  Sung-Hun Kim ,  Da-Hye Shim ,  Soon-Hwan Hong

IPC: G09G3/3258 ,  G09G3/3266

Abstract: An electroluminescent display device includes a display panel including a display region, which includes a plurality of pixel arrangement regions and a plurality of scan circuit regions between the plurality of pixel arrangement regions, and a non-display region around the display region; a scan driving circuit formed in the plurality of scan circuit regions, and a clock signal line transferring a clock signal, and a first voltage line and a second voltage line located at both sides of the clock signal line, the clock signal line and the first and second voltage lines being located in the scan circuit region, wherein the first voltage line transfers a low potential driving voltage which is supplied to a cathode corresponding to the display region.

公开(公告)号：US09075269B2

公开(公告)日：2015-07-07

申请号：US14080809

申请日：2013-11-15

Applicant: LG Display Co., Ltd.

Inventor： Kyung-Mo Son ,  Jae-Kyun Lee ,  Sung-Chol Yi ,  Taek-Jun Jung ,  Sun-Ju Ku ,  Soon-Hwan Hong ,  Sang-Su Jang ,  Jun-Young Jeong ,  Eun-Hye Lee

IPC: G02F1/13 ,  G02F1/1343 ,  G02F1/1339

CPC classification number: G02F1/134336 ,  G02F1/13394 ,  G02F1/134309 ,  G02F2001/13396

Abstract: An array substrate includes a substrate; gate lines over the substrate along a first direction; data lines over the substrate along a second direction and crossing the gate lines to define pixel regions; a thin film transistor at each crossing portion of the gate and data lines; an insulating layer covering the thin film transistor and having a flat top surface; a common electrode on the insulating layer all over the substrate; a common line on the common electrode; a passivation layer on the common line; and a pixel electrode on the passivation layer in each pixel region and connected to the thin film transistor, the pixel electrode including electrode patterns, wherein the passivation layer has a step height at a top surface of the passivation layer due to the plurality of common lines.

Abstract translation: 阵列基板包括基板; 沿着第一方向在基板上方的栅极线; 数据线沿着第二方向穿过衬底，并与栅极线交叉以限定像素区域; 栅极和数据线的每个交叉部分处的薄膜晶体管; 覆盖薄膜晶体管并具有平坦的顶表面的绝缘层; 在整个衬底上的绝缘层上的公共电极; 公共电极上的共同线路; 公共线上的钝化层; 以及像素电极，其在每个像素区域中的钝化层上并连接到所述薄膜晶体管，所述像素电极包括电极图案，其中所述钝化层由于所述多个公共线而在所述钝化层的顶表面处具有台阶高度 。