CIRCUITS AND METHODS FOR SLEW RATE CONTROL OF SWITCHED CAPACITOR REGULATORS

    公开(公告)号:US20190265743A1

    公开(公告)日:2019-08-29

    申请号:US15903974

    申请日:2018-02-23

    Abstract: Circuits comprising: a first capacitor(C1); a first switch(S1) having a first side coupled to a VIN and a second side coupled to a first side of C1; a second switch(S2) having a first side coupled to the second side of S1; a third switch(S3) having a first side coupled to a second side of S2 and a second side coupled to a second side of C1; a fourth switch(S4) having a first side coupled to a second side of S3 and a second side coupled to a VSUPPLY, wherein: in a first state, S1 and S3 are off, and S2 and S4 are on; in a second state, S1 and S3 are on, and S2 and S4 are off; and at least one of a control of S1, a control of S2, a control of S3, and a control of S4 is coupled to a time-varying-slew-rate signal.

    CIRCUITS FOR THREE-LEVEL BUCK REGULATORS
    12.
    发明申请

    公开(公告)号:US20190214905A1

    公开(公告)日:2019-07-11

    申请号:US15868496

    申请日:2018-01-11

    CPC classification number: H02M3/158 H02M1/32

    Abstract: An inductor; a first switch having a first side connected to a first voltage source (VS1); a second switch having a first side connected to a second side of the first switch (2SS1), and a second side connected to a first side of the inductor (1SI); a third switch having a first side connected to the 1SI; a fourth switch having a first side connected to a second side of the third switch (2SS3), and a second side connected to a second voltage source (VS2); a fifth switch having a first side connected to the 1SI, and a second side connected to the VS1 and/or the VS2; a first capacitor having a first side connected to the 2SS1, and a second side connected to the 2SS3; and a second capacitor having a first side connected to a second side of the inductor, and a second side connected to the VS2.

    Circuits for three-level buck regulators

    公开(公告)号:US10355593B1

    公开(公告)日:2019-07-16

    申请号:US15868496

    申请日:2018-01-11

    Abstract: An inductor; a first switch having a first side connected to a first voltage source (VS1); a second switch having a first side connected to a second side of the first switch (2SS1), and a second side connected to a first side of the inductor (1SI); a third switch having a first side connected to the 1SI; a fourth switch having a first side connected to a second side of the third switch (2SS3), and a second side connected to a second voltage source (VS2); a fifth switch having a first side connected to the 1SI, and a second side connected to the VS1 and/or the VS2; a first capacitor having a first side connected to the 2SS1, and a second side connected to the 2SS3; and a second capacitor having a first side connected to a second side of the inductor, and a second side connected to the VS2.

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