公开(公告)号：US10432214B2

公开(公告)日：2019-10-01

申请号：US16190168

申请日：2018-11-14

Applicant: MEDIATEK INC.

Inventor： Chan-Hsiang Weng ,  Tien-Yu Lo

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/10 ,  H03M1/06

Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.

公开(公告)号：US10141948B2

公开(公告)日：2018-11-27

申请号：US15586332

申请日：2017-05-04

Applicant: MEDIATEK Inc.

Inventor： Chan-Hsiang Weng ,  Tien-Yu Lo

IPC: H03M3/00

Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.