公开(公告)号：US07473610B2

公开(公告)日：2009-01-06

申请号：US12047457

申请日：2008-03-13

申请人： Francois Pagette

发明人： Francois Pagette

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66318 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

摘要： A method of forming a heterojunction bipolar transistor (HBT) device is disclosed. The method includes forming an intrinsic base layer over a collector layer; forming a sacrificial block structure over the intrinsic base layer; formina a sacrificial spacer layer surrounding top and side surfaces of the sacrificial block structure; forming an extrinsic base layer over the intrinsic layer and adjacent the sacrificial spacer layer; forming a protective layer over the extrinsic base layer; removing the sacrificial spacer layer and implanting a ring shaped dopant profile within an upper portion of the collector layer, wherein the ring shaped collector implant structure corresponds to a pattern of the removed protective layer; removing the sacrificial block structure so as to expose an emitter opening; forming sidewall spacers within the emitter opening; and forming an emitter within the emitter opening, wherein the ring shaped dopant profile is disposed so as to be aligned beneath a perimeter portion of the emitter.

摘要翻译： 公开了一种形成异质结双极晶体管（HBT）器件的方法。 该方法包括在集电极层上形成本征基层; 在本征基层上形成牺牲块结构; 围绕牺牲块结构的顶表面和侧表面的牺牲间隔层; 在所述本征层上形成并邻近所述牺牲间隔层的非本征基层; 在外基层上形成保护层; 去除所述牺牲间隔层并在所述集电极层的上部内注入环形掺杂剂轮廓，其中所述环形集电体注入结构对应于所述去除的保护层的图案; 去除牺牲块结构以暴露发射器开口; 在发射器开口内形成侧壁间隔物; 以及在所述发射器开口内形成发射器，其中所述环形掺杂剂轮廓被设置成在所述发射体的周边部分下方对齐。

公开(公告)号：US07394113B2

公开(公告)日：2008-07-01

申请号：US11460013

申请日：2006-07-26

申请人： Francois Pagette ,  Anna Topol

发明人： Francois Pagette ,  Anna Topol

IPC分类号： H01L29/70

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.

摘要翻译： 本文的实施方案提供了用于异质结双极晶体管（HBT）的自对准方案的结构，方法等。 提供了一种HBT，其包括非本征基极，在外部基极上的第一自对准硅化物层，以及位于第一自对准硅化物层上方的氮化物蚀刻停止层。 第一自对准硅化物层和氮化物蚀刻停止层之间还包括连续层，其中连续层可以包括氧化物。 HBT还包括邻近连续层的间隔物，其中间隔物和连续层将外部碱基与发射体接触分开。 此外，提供了发射器，其中发射器的高度小于或等于外部基极的高度。 此外，第二自对准硅化物层在发射极之上，其中第二硅化物层的高度小于或等于第一硅化物层的高度。

公开(公告)号：US20070272946A1

公开(公告)日：2007-11-29

申请号：US11838941

申请日：2007-08-15

申请人： Francois Pagette

发明人： Francois Pagette

IPC分类号： H01L29/739

CPC分类号： H01L29/7378 ,  H01L29/66318

摘要： Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

公开(公告)号：US20070235762A1

公开(公告)日：2007-10-11

申请号：US11308541

申请日：2006-04-04

申请人： Francois Pagette

发明人： Francois Pagette

IPC分类号： H01L31/00

CPC分类号： H01L29/7378 ,  H01L29/66318

摘要： Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

摘要翻译： 公开了一种改进的异质结双极晶体管（HBT）结构和形成具有分级锗型材的硅 - 锗发射极层的结构的方法。 分级锗浓度在发射极层的中性区域产生准漂移场。 该准漂移场引发发射极层内的价带隙分级，以加速空穴从基极层通过发射极层的移动。 通过发射极层从基极层加速孔的移动减少了发射极延迟时间，从而增加了截止频率（f T T T T）和最大振荡频率（f MAX） SUB>）。

公开(公告)号：US07217988B2

公开(公告)日：2007-05-15

申请号：US10709905

申请日：2004-06-04

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Francois Pagette ,  Christopher M. Schnabel ,  Anna W. Topol

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Francois Pagette ,  Christopher M. Schnabel ,  Anna W. Topol

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。

公开(公告)号：US08405127B2

公开(公告)日：2013-03-26

申请号：US12034210

申请日：2008-02-20

申请人： Jack O. Chu ,  Francois Pagette

发明人： Jack O. Chu ,  Francois Pagette

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/45 ,  H01L29/66242

摘要： In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base.

摘要翻译： 在一个实施例中，本发明是用于制造异质结双极晶体管的方法和装置。 异质结双极晶体管的一个实施例包括集电极层，形成在集电极层上的基极区域，形成在基极区域和集电极层顶部的自对准发射极，围绕发射极的聚锗外基极和金属 形成在外在基础上的锗化物层。

公开(公告)号：US07679164B2

公开(公告)日：2010-03-16

申请号：US11620242

申请日：2007-01-05

申请人： Francois Pagette ,  Christian Lavoie ,  Anna Topol

发明人： Francois Pagette ,  Christian Lavoie ,  Anna Topol

IPC分类号： H01L27/102

CPC分类号： H01L29/737 ,  H01L29/0821 ,  H01L29/66242

摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.

摘要翻译： 本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。 本发明的实施例还提供了制造该方法的方法。

公开(公告)号：US20090283801A1

公开(公告)日：2009-11-19

申请号：US12535310

申请日：2009-08-04

申请人： Francois Pagette ,  Kathryn Turner Schonenberg

发明人： Francois Pagette ,  Kathryn Turner Schonenberg

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

摘要： Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

公开(公告)号：US20090202952A1

公开(公告)日：2009-08-13

申请号：US12028861

申请日：2008-02-11

申请人： David W. Abraham ,  Steven E. Steen ,  Nicholas C.M. Fuller ,  Francois Pagette

发明人： David W. Abraham ,  Steven E. Steen ,  Nicholas C.M. Fuller ,  Francois Pagette

IPC分类号： G03F7/26

CPC分类号： H01L21/0337 ,  H01L21/32139

摘要： A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.

摘要翻译： 实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征，初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物，然后移除所述第一组图案特征，以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代，随后移除随后的一组图案化特征，其中给定的一组图案化特征基于相关联的一组侧壁的几何形状 间隔物在其之前形成，并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。

公开(公告)号：US07388237B2

公开(公告)日：2008-06-17

申请号：US11870437

申请日：2007-10-11

申请人： Francois Pagette

发明人： Francois Pagette

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66318 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

摘要： A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the collector layer, wherein the ring shaped collector implant structure is disposed so as to be aligned beneath a perimeter portion of the emitter.

摘要翻译： 双极晶体管结构包括在集电极层上形成的本征基极层，在本征基极层上形成的发射体，以及在本征层上形成并邻近发射极的非本征基极层。 环形收集器植入结构形成在集电器层的上部内，其中环形收集器植入结构被设置成在发射器的周边部分下方对准。