公开(公告)号：US20160141020A1

公开(公告)日：2016-05-19

申请号：US14543910

申请日：2014-11-18

Applicant: MEDIATEK INC.

Inventor： Rei-Fu Huang ,  Shih-Huang Huang

IPC: G11C11/418 ,  G11C29/00 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419 ,  G11C29/10 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time.

Abstract translation: 静态随机存取存储器（SRAM）包括存储单元阵列，行解码器，多个字线驱动器和仲裁器。 存储单元阵列包括多个存储单元行，其中存储单元行分别由多个字线使能。 行解码器被布置为根据行地址来声明其中一个存储单元行。 多个字线驱动器各自耦合到行解码器和存储单元行之一。 仲裁器被布置成防止同一字线上的多个存储器单元被同时访问。